Compression circuitry for generating an encoded bitstream from a plurality of video frames

Abstract

Data is discrete cosine transformed and streamed to a processor where quantized and inverse quantized blocks are generated. A second streaming data connection streams the inverse quantized blocks to an inverse discrete cosine transform block to generate reconstructed prediction error macroblocks. An addition circuit adds each reconstructed prediction error macroblock and its corresponding predictor macroblock to generate a respective reconstructed macroblock. The quantized macroblocks are zig-zag scanned, run level coded and variable length coded to generate and encoded bitstream.

1 . A decoder circuit, comprising:
 a processor configured to inverse quantize macroblocks to generate inverse quantized macroblocks;   an inverse discrete cosine transformation circuit that processes the inverse quantized macroblocks from the processor to generate IDCT transformed macroblocks; and   an addition circuit that adds a single IDCT transformed macroblock and a corresponding predictor macroblock to generate a reconstructed picture macroblock.   
   
   
       2 . The decoder circuit of  claim 1 , further comprising a delay buffer for storing the corresponding predictor macroblocks. 
   
   
       3 . The decoder circuit of  claim 2 , wherein a motion estimation engine provides the corresponding predictor macroblocks to the delay buffer. 
   
   
       4 . The decoder circuit of  claim 3 , further comprising a first streaming data connection for streaming the inverse quantized macroblocks from the processor to the IDCT circuit. 
   
   
       5 . The decoder circuit of  claim 4 , wherein the IDCT circuit processes data at a rate determined by the arrival of data from the relevant data connection. 
   
   
       6 . The decoder circuit of  claim 5 , wherein the IDCT circuit processes data at a rate determined by a handshake control signal. 
   
   
       7 . The decoder circuit of  claim 6 , further comprising a macroblock memory to store the reconstructed picture macroblocks. 
   
   
       8 . A method for decoding an encoded bitstream, comprising:
 inverse quantizing decoded macroblocks in a processor to generate inverse quantized macroblocks;   generating inverse discrete cosine transformation (IDCT) transformed macroblocks from the inverse quantized macroblocks; and   adding a single IDCT transformed macroblock and a corresponding predictor macroblock to generate a reconstructed picture macroblock.   
   
   
       9 . The method according to  claim 8 , further comprising storing the corresponding predictor macroblocks in a delay buffer. 
   
   
       10 . The method according to  claim 9 , further comprising receiving the corresponding predictor macroblocks from a motion estimation engine. 
   
   
       11 . The method according to  claim 10 , further comprising streaming the inverse quantized macroblocks from the processor to the IDCT circuit. 
   
   
       12 . The method according to  claim 11 , wherein generating the IDCT transformed macroblocks takes place at a rate determined by the arrival of data. 
   
   
       13 . The method according to  claim 12 , wherein generating the IDCT transformed macroblocks takes place at a rate determined by a handshake control signal. 
   
   
       14 . The method according to  claim 13 , further comprising storing the reconstructed picture macroblocks in a macroblock memory. 
   
   
       15 . A video compression circuit, comprising:
 a discrete cosine transform (DCT) circuit for accepting prediction error macroblocks and generating DCT transformed macroblocks;   a processor being configured to quantize the DCT transformed macroblocks to generate quantized macroblocks, and to inverse quantize the quantized macroblocks to generate inverse quantized macroblocks;   an inverse discrete cosine transform (IDCT) circuit, wherein the IDCT circuit transforms the inverse quantized macroblocks to generate reconstructed prediction error macroblocks; and   an addition circuit for adding a single reconstructed prediction error macroblock and a corresponding predictor macroblock to generate respective reconstructed macroblocks for use in the encoding of other macroblocks.   
   
   
       16 . The compression circuit of  claim 15 , further comprising means for zig-zag scanning, run level coding and variable length coding the quantized macroblocks to generate an encoded bitstream. 
   
   
       17 . The compression circuit of  claim 16 , wherein the means for zig-zag scanning and run length coding is the processor configured to implement the zig-zag scanning and run length coding, and the means for variable length coding is a hardware VLC packer. 
   
   
       18 . The compression circuit of  claim 17 , further comprising:
 a first streaming data connection for streaming the DCT transformed macroblocks from the DCT transformation circuit to the processor;   a second streaming data connection for streaming the inverse quantized macroblocks from the processor to the IDCT transformation circuit; and   a third streaming data connection for streaming the run length coded data from the processor to the hardware VLC packer.   
   
   
       19 . The compression circuit of  claim 18 , wherein the DCT circuit, the IDCT circuit, and the hardware VLC packer process data at a rate determined by the arrival of data from the relevant data connection. 
   
   
       20 . The compression circuit according to  claim 19 , wherein the DCT circuit, the IDCT circuit, and the hardware VLC packer process data at a rate determined by a handshake control signal. 
   
   
       21 . The compression circuit according to  claim 20 , further comprising a motion estimation engine for supplying the prediction error macroblocks to the DCT circuit. 
   
   
       22 . The compression circuit according to  claim 21 , further comprising a macroblock memory for storing the reconstructed macroblocks. 
   
   
       23 . A method of generating a compressed video bitstream, the method comprising:
 generating DCT transformed macroblocks by applying prediction error macroblocks to a discrete cosine transform (DCT) circuit;   quantizing the DCT transformed macroblocks to generate quantize macroblocks;   inverse quantizing the quantize macroblocks to generate inverse quantize macroblocks;   generating reconstructed prediction error macroblocks by applying the inverse quantize macroblocks to a IDCT circuit; and   adding a single reconstructed prediction error macroblock and a corresponding predictor macroblock to generate respective reconstructed macroblocks for use in the encoding of other macroblocks.   
   
   
       24 . The method according to  claim 23 , further comprising generating an encoded bitstream by zig-zag scanning, run level coding and variable length coding the quantized macroblocks. 
   
   
       25 . The method according to  claim 24 , wherein generating the encoded bitstream by zig-zag scanning and run length coding the quantized macroblocks is performed by the processor configured to implement the zig-zag scanning and run length coding, and by variable length coding the run length coded macroblocks in a hardware VLC packer. 
   
   
       26 . The method according to  claim 25 , further comprising:
 streaming the DCT transformed macroblocks from the DCT transformation circuit to the processor;   streaming the inverse quantized macroblocks from the processor to the IDCT transformation circuit; and   streaming the run length coded data to the hardware VLC packer.   
   
   
       27 . The method according to  claim 26 , wherein generating the DCT transformed macroblocks, generating the reconstructed prediction error macroblocks, and generating the encoded bitstream take place at a rate determined by the arrival of data from the relevant data connection. 
   
   
       28 . The method according to  claim 27 , wherein generating the DCT transformed macroblocks, generating the reconstructed prediction error macroblocks, and generating the encoded bitstream takes place at a rate determined by a handshake control signal. 
   
   
       29 . The method according to  claim 28 , further comprising receiving the prediction error macroblocks from a motion estimation engine. 
   
   
       30 . The method according to  claim 29 , further comprising storing the reconstructed macroblocks in a macroblock memory. 
   
   
       31 . An encoder/decoder circuit, comprising:
 a discrete cosine transform (DCT) circuit to generate DCT transformed macroblocks from prediction error macroblocks;   a processor configured to quantize the DCT transformed macroblocks to generate quantized macroblocks, and to inverse quantize the quantized macroblocks to generate inverse quantized macroblocks;   an inverse discrete cosine transform (IDCT) circuit to transform the inverse quantized macroblocks to generate reconstructed prediction error macroblocks;   an addition circuit to add a single reconstructed prediction error macroblock and a corresponding predictor macroblock to generate respective reconstructed macroblocks; and   a control circuit to configure the encoder/decoder circuit to encode or decode a bitstream.   
   
   
       32 . The encoder/decoder of  claim 31 , wherein the encoder/decoder circuit configured for decoding mode uses the processor configured to inverse quantize macroblocks, the IDCT circuit, and the addition circuit to generate the reconstructed macroblocks. 
   
   
       33 . The encoder/decoder of  claim 32 , further comprising means for zig-zag scanning, run level coding and variable length coding the quantized macroblocks to generate an encoded bitstream. 
   
   
       34 . The encoder/decoder of  claim 33 , wherein the means for zig-zag scanning and run length coding is the processor configured to implement the zig-zag scanning and run length coding, and the means for variable length coding is a hardware VLC packer. 
   
   
       35 . The encoder/decoder of  claim 34 , further comprising a delay buffer for storing the corresponding predictor macroblocks. 
   
   
       36 . The encoder/decoder of  claim 35 , wherein a motion estimation engine provides the corresponding predictor macroblocks to the delay buffer. 
   
   
       37 . The encoder/decoder of  claim 36 , further comprising:
 a first streaming data connection for streaming DCT transformed macroblocks to the processor;   a second streaming data connection for streaming the inverse quantized macroblocks from the processor to the IDCT circuit; and   a third streaming data connection for streaming the run length coded data from the processor to the hardware VLC packer.   
   
   
       38 . The encoder/decoder of  claim 37 , wherein the DCT circuit, the IDCT circuit, and the hardware VLC packer process data at a rate determined by the arrival of data from the relevant data connection. 
   
   
       39 . The encoder/decoder of  claim 38 , wherein the DCT circuit, the IDCT circuit, and the hardware VLC packer process data at a rate determined by a handshake control signal. 
   
   
       40 . The encoder/decoder of  claim 39 , further comprising a macroblock memory to store the reconstructed macroblocks. 
   
   
       41 . A method for encoding and decoding in an encoder/decoder circuit having a control circuit to configure the encoder/decoder circuit for encoding or decoding mode, comprising:
 generating DCT transformed macroblocks by applying prediction error macroblocks to a discrete cosine transform (DCT) circuit;   quantizing the DCT transformed macroblocks to generate quantized macroblocks;   inverse quantizing the quantized macroblocks to generate inverse quantized macroblocks;   generating reconstructed prediction error macroblocks by applying the inverse quantized macroblocks to the IDCT circuit; and   adding the reconstructed prediction error macroblocks and corresponding predictor macroblocks to generate respective reconstructed macroblocks;   wherein the reconstructed macroblocks are useful either as decoded reconstructed picture macroblocks or for encoding other macroblocks.   
   
   
       42 . The method according to  claim 41 , further comprising generating an encoded bitstream by zig-zag scanning, run level coding and variable length coding the quantized macroblocks. 
   
   
       43 . The method according to  claim 42 , wherein generating the encoded bitstream by zig-zag scanning and run length coding the quantized macroblocks is performed by the processor configured to implement the zig-zag scanning and run length coding, and by variable length coding the run length coded macroblocks in a hardware VLC packer. 
   
   
       44 . The method according to  claim 43 , further comprising storing the corresponding predictor macroblocks in a delay buffer. 
   
   
       45 . The method according to  claim 44 , further comprising receiving the corresponding predictor macroblocks and the prediction error macroblocks from a motion estimation engine. 
   
   
       46 . The method according to  claim 45 , further comprising:
 streaming the DCT transformed macroblocks to the processor;   streaming the inverse quantized macroblocks from the processor to the IDCT circuit; and   streaming the run length coded data from the processor to the hardware VLC packer.   
   
   
       47 . The method according to  claim 46 , wherein generating the DCT transformed macroblocks, generating the reconstructed prediction error macroblocks, and generating the encoded bitstream take place at a rate determined by the arrival of data from the relevant data connection. 
   
   
       48 . The method according to  claim 47 , wherein generating the DCT transformed macroblocks, generating the reconstructed prediction error macroblocks, and generating the encoded bitstream take place at a rate determined by a handshake control signal.