Multi-component electronic package with planarized embedded-components substrate

Abstract

An electronic multi-component package is assembled by placing multiple electronic components within multiple openings of a package substrate, then depositing and curing adhesive filler in gaps between the components and the inner peripheries of the openings. Circuit features, including conductive interconnects, are formed by thin-film photolithography over both front and back surfaces of the package substrate. Preformed conductive vias through the package substrate provide electrical connection between circuit features on opposite substrate surfaces. Additional electronic components may be attached to conductive lands on at least one side of the package. The circuit features also include contact pads for external package connections, such as in a ball-grid-array or equivalent structure.

1 . A method of assembling an multi-component electronic package, comprising:
 providing a package substrate having defined front and back surfaces, with conductive vias through the package substrate providing electrical connections between the front and back surfaces, and with multiple openings in the package substrate adapted to receive electronic components;   securing the package substrate on a vacuum support;   placing multiple electronic components within the multiple openings of the package substrate, the electronic components being secured in place by the vacuum support, each electronic component being spaced from an inner periphery of its corresponding opening of the package substrate by a gap;   depositing an adhesive filler material within the gap and then curing the adhesive filler material, such that the electronic components within the openings are permanently secured to the package substrate; and   forming circuit features in one or more layers on both front and back surfaces of the package substrate, circuit features on opposite surfaces of the package substrate being electrically connected to each other by means of the conductive vias through the package substrate, the circuit features including conductive interconnects that are electrically connected to the multiple electronic components, the circuit features on at least one surface of the package substrate including a set of contact pads defining external connection locations for the assembled multi-component electronic package.   
     
     
         2 . The method as in  claim 1 , wherein the package substrate comprises a dielectric material with metallic vias therethrough. 
     
     
         3 . The method as in  claim 1 , wherein at least one of the multiple electronic components placed within the openings of the package substrate is an integrated circuit (IC) die. 
     
     
         4 . The method as in  claim 3 , wherein the IC die has an active surface and the IC die is placed in an opening of the package substrate with its active surface coinciding with designated front surface of the package substrate. 
     
     
         5 . The method as in  claim 1 , wherein the circuit features are formed by photolithography, with deposition a thin-film feature layer and a mask layer over the feature layer, patterning and etching of the feature layer using the mask layer, removal of the mask layer, and repeating to pattern additional feature layers. 
     
     
         6 . The method as in  claim 1 , wherein the circuit features include integrated passive circuit elements. 
     
     
         7 . The method as in  claim 1 , wherein the circuit features are successive formed first on one surface of the package substrate and then on the other surface of the package substrate. 
     
     
         8 . The method as in  claim 1 , wherein the circuit features formed on the package substrate include conductive lands and the method further comprises attaching additional electronic components onto the designated front surface of the package substrate with electrical connections to the conductive lands. 
     
     
         9 . The method as in  claim 8 , further comprising providing a protective covering over the additional electronic components. 
     
     
         10 . The method as in  claim 1 , wherein the set of contact pads are formed as circuit features on a designated back surface of the package substrate. 
     
     
         11 . The method as in  claim 10 , wherein the set of contact pads form a package contact structure selected from the group consisting of a land-grid-array, ball-grid-array and pin-grid-array. 
     
     
         12 . The method as in  claim 1 , wherein the package substrate is a wafer for assembling multiple packages, and the method, after forming the circuit features, further includes segmenting the wafer into individual assembled packages. 
     
     
         13 . A multi-component electronic package, comprising:
 a package substrate having designated front and back surfaces with conductive vias through the substrate;   multiple electronic components embedded within the package substrate and secured thereto by a cured adhesive material; and   one or more layers of circuit features on both front and back surfaces of the package substrate, circuit features on opposite surfaces of the package substrate being electrically connected to each other by means of the conductive vias through the package substrate, the circuit features including conductive interconnects that are electrically connected to the multiple electronic components, the circuit features on at least one surface of the package substrate including a set of contact pads defining external connection locations for the electronic multi-component package.   
     
     
         14 . The package as in  claim 13 , wherein the package substrate comprises a dielectric material with metallic vias therethrough. 
     
     
         15 . The package as in  claim 13 , wherein at least one of the multiple electronic components embedded within the package substrate is an integrated circuit (IC) die. 
     
     
         16 . The package as in  claim 13 , wherein the circuit features include integrated passive circuit elements. 
     
     
         17 . The package as in  claim 13 , wherein the circuit features formed on the package substrate include conductive lands and the package further comprises additional electronic components attached to the designated front surface of the package substrate with electrical connections to the conductive lands. 
     
     
         18 . The package as in  claim 17 , further comprising a protective covering over the additional electronic components. 
     
     
         19 . The package as in  claim 13 , wherein the set of contact pads form a package contact structure selected from the group consisting of a land-grid-array, ball-grid-array and pin-grid-array.