Timing controller and method of generating timing signals

Abstract

A timer controller and method of generating timing signals uses a synchronization signal and a clock signal to generate a timing signal by counting the clock signal only after the synchronization signal has changed states. In a display requiring a dot or line counter having n digits to meet the requirement of display resolution, it is possible to use a counter with k digits to generate a start signal, with 0≦k<n. In particular, a start signal can be generated even without a counter.

1 . A method for generating timing signals based upon a first periodic signal and a second periodic signal, the first periodic signal having a first signal cycle in a time unit, wherein the second periodic signal has a second signal cycle between N′=2 (n-1)  times and N=2 n  times the first signal cycle in a time unit, with n being a predetermined positive integer, said method comprising the steps of:
 determining when the second periodic signal changes from state one to state two; and   generating a timing signal based on the second periodic signal, the timing signal having a first edge and a second edge, wherein a distance in the time units from the first edge and said change in the second periodic signal is equal to L times the first signal cycle, with L being a positive integer such that 0≦L<N′, and wherein the timing signal is generated based on a count of the first signal cycle from a counter having k digits, with 0≦k<n and 0≦L≦(2 k −1).   
   
   
       2 . The method of  claim 1 , wherein the first periodic signal is a clock signal, the second periodic signal is a horizontal synchronization signal, and the timing signal is a horizontal start signal in a display panel. 
   
   
       3 . The method of  claim 1 , wherein the first periodic signal is a horizontal synchronization signal, the second periodic signal is a vertical synchronization signal, and the timing signal is a vertical start signal in a display panel. 
   
   
       4 . The method of  claim 1 , wherein state one is representative of a first voltage level of the second periodic signal and state two is representative of a second voltage level of the second period signal, and wherein the second voltage level is lower than the first voltage level. 
   
   
       5 . The method of  claim 1 , wherein the second periodic signal changes from state one to state two at a first position in the second signal cycle, and the second period signal also changes from state two to state one at a second position within said second signal cycle, and wherein the first edge of the timing signal is located before the second position and the second edge of the timing signal is located after the second position. 
   
   
       6 . The method of  claim 1 , wherein the second periodic signal changes from state one to state two at a first position in the second signal cycle, and the second period signal also changes from state two to state one at a second position within said second signal cycle, and wherein both the first edge and the second edge of the timing signal are located before the second position. 
   
   
       7 . The method of  claim 1 , wherein the second periodic signal changes from state one to state two at a first position in the second signal cycle, and the second period signal also changes from state two to state one at a second position within said second signal cycle, and wherein both the first edge and the second edge of the timing signal are located after the second position. 
   
   
       8 . The method of  claim 1 , wherein the second periodic signal changes from state one to state two at a first position in the second signal cycle, and the second period signal also changes from state two to state one at a second position within said second signal cycle, and wherein the first edge of the timing signal is located at the first position and the second edge of the timing signal is located at the second position. 
   
   
       9 - 13 . (canceled)