US2008122104A1PendingUtilityA1
Damascene interconnect structure having air gaps between metal lines and method for fabricating the same
Est. expiryNov 27, 2026(~0.4 yrs left)· nominal 20-yr term from priority
Inventors:Shuo-Ting Yan
H10W 20/495H10W 20/081H10W 20/47H10W 20/072H10W 20/46
50
PatentIndex Score
0
Cited by
0
References
0
Claims
Abstract
An exemplary damascene interconnect structure includes a substrate ( 20 ), a first dielectric layer ( 21 ) on the substrate, a plurality of trenches ( 27 ) formed in the first dielectric layer, and a plurality of metal lines ( 24 ) filled in the trenches. The first dielectric layer includes multi sub-dielectric layers ( 211, 212, 213 ). Wherein a plurality of air gaps ( 28 ) are maintained between the metal lines and at least one of the sub-dielectric layers. A method for fabricating the damascene interconnect structure is also provided.
Claims
exact text as granted — not AI-modified1 . A damascene interconnect structure, comprising:
a substrate; a first dielectric layer on the substrate, the first dielectric layer comprising a plurality of sub-dielectric layers; a plurality of trenches formed in the first dielectric layer; and a plurality of metal lines filled in the trenches; wherein a plurality of air gaps are maintained between the metal lines and at least one of the sub-dielectric layers.
2 . The damascene interconnect structure as claimed in claim 1 , wherein the plurality of sub-dielectric layers comprises a first, a second, and a third sub-dielectric layers arranged in that order from bottom to top, and the air gaps are maintained between the metal lines and the second sub-dielectric layer.
3 . The damascene interconnect structure as claimed in claim 2 , wherein the first and the third sub-dielectric layers are silicon nitride layers, and the second sub-dielectric layer is a silicon oxide layer.
4 . The damascene interconnect structure as claimed in claim 2 , wherein the first, the second, and the third sub-dielectric layers are silicon nitride layers, and a density of each of the first and the third sub-dielectric layers is greater than that of the second sub-dielectric layer.
5 . The damascene interconnect structure as claimed in claim 2 , wherein the first, the second, and the third sub-dielectric layers are silicon oxide layers, and a density of each of the first and the third sub-dielectric layers is greater than that of the second sub-dielectric layer.
6 . The damascene interconnect structure as claimed in claim 1 , further comprising a capping layer and a second dielectric layer, the capping layer covering the first dielectric layer and the metal lines, and the second dielectric layer covering the capping layer.
7 . The damascene interconnect structure as claimed in claim 2 , wherein material of the metal lines is at least one of copper, silver, aluminum, and an alloy comprising any one or more of copper, aluminum and silver.
8 . A method for fabricating a damascene interconnect structure, the method comprising:
providing a substrate; depositing a multilayer dielectric film on the substrate; forming a patterned photoresist on the multilayer dielectric film; etching the multilayer dielectric film to form a plurality of trenches, a portion of each of the trenches having an enlarged width at each of sidewalls thereof; filling the trenches with conductive metal to form conductive lines such that air is trapped in extremities of the enlarged width portions of the trenches.
9 . The method for fabricating a damascene interconnect structure as claimed in claim 8 , wherein the conductive metal filled in the trenches is formed by means of physical vapor deposition.
10 . The method for fabricating a damascene interconnect structure as claimed in claim 8 , wherein the multilayer dielectric film comprises a first, a second, and a third sub-dielectric layer, and the air is trapped between the second sub-dielectric layer and the conductive lines.
11 . The method for fabricating a damascene interconnect structure as claimed in claim 10 , wherein the first and the third sub-dielectric layer are silicon nitride layers, and the second sub-dielectric layer is a silicon oxide layer.
12 . The method for fabricating a damascene interconnect structure as claimed in claim 10 , wherein all three sub-dielectric layers are silicon nitride layers or silicon oxide layers, and a deposition rate of each of the first and the third sub-dielectric layers is greater than that of the second sub-dielectric layer.
13 . The method for fabricating a damascene interconnect structure as claimed in claim 8 , wherein the multilayer dielectric layer is etched by a wet etching method.
14 . The method for fabricating a damascene interconnect structure as claimed in claim 13 , wherein an etchant of the wet etching method is a mixture of hydrogen fluoride and ammonium fluoride.
15 . The method for fabricating a damascene interconnect structure as claimed in claim 8 , wherein the multilayer dielectric layer is etched by a dry etching method.
16 . The method for fabricating a damascene interconnect structure as claimed in claim 15 , wherein an etchant of the dry etching method is a mixture of sulfur hexafluoride and carbon tetrafluoride.
17 . The method for fabricating a damascene interconnect structure as claimed in claim 8 , further comprising forming a capping layer covering the multilayer dielectric layer and the conductive lines, and forming a dielectric layer on the capping layer.
18 . The method for fabricating a damascene interconnect structure as claimed in claim 8 , wherein material of the conductive lines is at least one of copper, aluminum, silver, and an alloy comprising any one or more of copper, aluminum and silver.Join the waitlist — get patent alerts
Track US2008122104A1 — get alerts on status changes and closely related new filings.
We store only your email — no account needed. See our privacy policy.