Silicon carrier having increased flexibility

Abstract

An apparatus and method providing flexibility to a silicon chip carrier which, in at least one embodiment, comprises multiple chips and a silicon chip carrier having thinned regions between some adjacent chips, thus, allowing for increased flexibility and reduced package warpage.

1 . A chip carrying apparatus for use in electronic devices, said apparatus comprising:
 a plurality of chips;   a chip carrier including interconnection regions allowing electrical interconnections between said chips and said chip carrier,   wherein the thickness of at least one localized area of said chip carrier is reduced compared to at least one other localized area of said chip carrier; and   a substrate.   
   
   
       2 . The apparatus according to  claim 1 , wherein said chip carrier is a silicon chip carrier. 
   
   
       3 . The apparatus according to  claim 2 , wherein said interconnections are solder microbumps. 
   
   
       4 . The apparatus according to  claim 2 , wherein said interconnections are permanent copper interconnections. 
   
   
       5 . The apparatus according to  claim 2 , wherein said silicon chip carrier further comprises through-vias. 
   
   
       6 . The apparatus according to  claim 2 , wherein the reduced region is reduced to no more than about sixty percent of the original thickness. 
   
   
       7 . The apparatus according to  claim 2 , wherein the thickness of any wiring layers is not reduced. 
   
   
       8 . The apparatus according to  claim 2 , wherein walls to said reduced regions are formed by etching. 
   
   
       9 . The apparatus according to  claim 8  wherein said reduced regions are formed by a chemical etching process. 
   
   
       10 . The apparatus according to  claim 8 , wherein said etching comprises DRIE etching. 
   
   
       11 . The apparatus of according to  claim 2 , further comprising BEOL layers. 
   
   
       12 . The apparatus according to  claim 11 , wherein said reduced region comprises said BEOL layer. 
   
   
       13 . A method for manufacturing a chip carrying apparatus for use in electronic devices, said method comprising the steps of:
 creating interconnection regions in a chip carrier which allow electrical interconnections between said chip carrier and chips placed on said chip carrier,   reducing the thickness of at least one localized area of said chip carrier compared to at least one other localized are of said chip carrier   
   
   
       14 . The method according to  claim 13 , wherein said chip carrier is a silicon chip carrier. 
   
   
       15 . The method according to  claim 14 , wherein said interconnections are solder microbumps. 
   
   
       16 . The method according to  claim 14 , wherein said interconnections are permanent copper interconnections. 
   
   
       17 . The method according to  claim 14 , wherein said silicon chip carrier comprises through-vias. 
   
   
       18 . The method according to  claim 14 , wherein the reduced region is reduced to no more than about sixty percent of the original thickness. 
   
   
       19 . The method according to  claim 14 , wherein the thickness of any wiring layers is not reduced. 
   
   
       20 . The method according to  claim 14 , wherein walls to said reduced regions are formed by etching. 
   
   
       21 . The method according to  claim 20 , wherein said reduced regions are formed by a chemical etching process. 
   
   
       22 . The method according to  claim 20 , wherein said etching comprises DRIE etching. 
   
   
       23 . The method according to  claim 14 , wherein BEOL layers are used. 
   
   
       24 . The method according to  claim 23 , wherein said reduced region comprises said BEOL layer.