Integrated Circuit Package and a Method for Forming an Integrated Circuit Package

Abstract

A method of forming an integrated circuit package, such as a Flip Chip package, in which a void is provided in the underfill material in the central region of the package between the chip or die and the substrate on which the chip or die is mounted. This reduces delamination of the package as a result of moisture.

1 . A method of forming an integrated circuit package, the method comprising:
 providing a die having a central region and a periphery surrounding the central region;   providing a substrate to which the die is to be mounted;   attaching the die to the substrate using a plurality of bumps, the die being spaced from the substrate; and,   providing an underfill material in the space between the die and the substrate, leaving a void containing no underfill material between the die and the substrate in the central region of the die.   
   
   
       2 . The method according to  claim 1 , wherein providing the underfill material comprises introducing the underfill material from around the periphery of the die, the material not flowing into the space between the substrate and die below the central region of the die. 
   
   
       3 . The method according to  claim 1 , wherein the underfill material has a high viscosity. 
   
   
       4 . The method according to  claim 2 , wherein the underfill material has a viscosity of at least 50 Pa.s. 
   
   
       5 . The method according to  claim 1 , further comprising solidifying or curing the underfill material other than below the central region of the die. 
   
   
       6 . The method according to  claim 1 , wherein the underfill material has a high filler loading. 
   
   
       7 . The method according to  claim 6 , wherein the filler loading of the underfill material is at least 75%. 
   
   
       8 . The method according to  claim 1 , in which the underfill material comprises an epoxy based material. 
   
   
       9 . The method according to  claim 1 , wherein the underfill material encapsulates at least some of the bumps. 
   
   
       10 . The method according to  claim 1 , further comprising encapsulating the die, substrate and underfill material. 
   
   
       11 . An integrated circuit package comprising:
 a substrate;   a die having a central region and a periphery surrounding the central region, the die being attached to and spaced from the substrate; and   an underfill material between the substrate and the die, the underfill material not being provided in a region below the central region of the die thereby leaving a void below the central region.   
   
   
       12 . The integrated circuit package according to  claim 11 , wherein the underfill material comprises an epoxy based material. 
   
   
       13 . The integrated circuit package according to  claim 11 , wherein the underfill material has a high viscosity. 
   
   
       14 . The integrated circuit package according to  claim 13 , wherein the underfill material has a viscosity of at least 50 Pa.s. 
   
   
       15 . The integrated circuit package according to  claim 11 , wherein the underfill material has a high filler loading. 
   
   
       16 . The integrated circuit package according to  claim 15 , wherein the underfill material has a filler loading of at least 75%. 
   
   
       17 . The integrated circuit package according to  claim 11 , further comprising a plurality of bumps between the substrate and the die. 
   
   
       18 . The integrated circuit package according to  claim 17 , wherein the substrate comprises a wafer. 
   
   
       19 . The integrated circuit package according to  claim 17 , wherein the substrate comprises a circuit board. 
   
   
       20 . The integrated circuit package according to  claim 17 , wherein the substrate comprises a carrier. 
   
   
       21 . The integrated circuit package according to  claim 17 , further comprising an encapsulation layer encapsulating at least a portion of the die, underfill material, bumps and substrate.