Intergrated circuit device, chip, and method of fabricating the same

Abstract

A method of manufacturing an integrated circuit (IC) chip is provided. The method includes the following steps. First, a substrate is provided. The substrate is divided into an internal region and an external region by a die seal ring region. A plurality of circuit units is then formed in the internal region on the substrate. Thereafter, a dielectric layer is formed over the substrate, interconnects are formed in the dielectric layer within the internal region, and a plurality of bonding pad structures is formed in the dielectric layer within the external region. Finally, a cutting process is performed along a plurality of scribed lines on the substrate to form a plurality of chips. The bonding pad structures are exposed at the sides of each chip.

What is claimed is: 
     
         1 . An integrated circuit chip, comprising:
 a substrate including a front surface and a back surface, wherein the back surface corresponds to the front surface;   a plurality of circuit units and a plurality of interconnects disposed on the front surface of the substrate; and   a plurality of bonding pads including a plurality of conductive layers which are at least positioned at one side of the substrate, wherein the side extends from an upper surface of the front surface to the back surface.   
     
     
         2 . The integrated circuit chip of  claim 1 , wherein each bonding pad further comprises a plurality of connecting portions connecting the adjoining conductive layers. 
     
     
         3 . The integrated circuit chip of  claim 1 , wherein the connecting portions are shaped as cylinders or layers. 
     
     
         4 . The integrated circuit hip of  claim 3 , wherein the connecting portions are shaped as cylinders and arranged in an irregular or a regular way. 
     
     
         5 . The integrated circuit chip of  claim 4 , wherein the regular arrangement includes an alternate arrangement, a line-up arrangement, or a matrix arrangement. 
     
     
         6 . The integrated circuit chip of  claim 3 , wherein the connecting portions are shaped as layers and the size thereof is smaller than or equal to the adjoining conductive layers. 
     
     
         7 . The integrated circuit chip of  claim 1 , wherein the connecting portions are equally or unequally sized. 
     
     
         8 . An integrated circuit device, comprising:
 a substrate, divided into an internal region and an external region by a die seal ring region;   a plurality of circuit units, positioned in the internal region on the substrate;   a dielectric layer over the substrate;   a first conductive layer, disposed in the dielectric layer within the internal region and external region;   a second conductive layer, disposed in the dielectric layer within the internal region and external region;   a plurality of vias/connecting portions, disposed in the dielectric layer and electrically coupled with the first conductive layer and the second conductive layer,   wherein parts of the first conductive layer, the second conductive layer, and the vias/connecting portions disposed in the internal region constitute interconnects;   parts of the first conductive layer, the second conductive layer, and the vias/connecting portions disposed in the external region constitute a plurality of bonding pad structures.   
     
     
         9 . The integrated circuit device of  claim 8 , wherein the first conductive layer and the second conductive layer of each bonding pad structure extend from an edge of the die seal ring region to a scribed line region of the substrate. 
     
     
         10 . The integrated circuit device of  claim 8 , wherein the vias/connecting portions of each bonding pad are arranged in an irregular or a regular way. 
     
     
         11 . The integrated circuit device of  claim 10 , wherein the regular arrangement includes an alternate arrangement, a line-up arrangement, or a matrix arrangement. 
     
     
         12 . The integrated circuit device of  claim 8 , wherein the vias/connecting portions of each bonding pad are equally or unequally sized. 
     
     
         13 . The integrated circuit device of  claim 8 , wherein the vias/connecting portions of each bonding pad and the vias/connecting portions of the interconnects are equally or unequally sized. 
     
     
         14 . A method of manufacturing an integrated circuit chip, comprising the following steps:
 providing a substrate, wherein the substrate is divided into an internal region and an external region by a die seal ring region;   forming a plurality of circuit units in the internal region on the substrate;   forming a dielectric layer over the substrate, a plurality of interconnects in the dielectric layer within the internal region, and a plurality of first bonding pad structures in the dielectric layer within the external region; and   performing a cutting process along a plurality of scribed lines on the substrate to form a plurality of chips, wherein the first bonding pad structures are exposed at the sides of each chip.   
     
     
         15 . The method of  claim 14 , wherein the steps of forming the interconnects and the first bonding pad structures comprise:
 forming a plurality of conductive layers in the dielectric layer within the internal region and the external region;   forming a plurality of vias/connecting portions electrically coupled with the conductive layers in the dielectric layer within the internal region and the external region, wherein   parts of the conductive layers and the vias/connecting portions in the internal region constitute the interconnects, and   parts of the conductive layers and the vias/connecting portions in the external region constitute the first bonding pad structures.   
     
     
         16 . The method of  claim 14 , wherein the steps of forming the dielectric layer, the interconnects, and the first bonding pad structures comprise:
 forming the dielectric layer on the substrate;   forming a plurality of trenches and a plurality of via openings/openings in the dielectric layer; and   filling a conductive material into the trenches and the via openings/openings to form the conductive layers and the vias/connecting portions.   
     
     
         17 . The method of  claim 15 , wherein the steps of forming the interconnects and the first bonding pad structures comprise:
 forming a first part of the dielectric layer on the substrate;   forming the conductive layers on the first part of the dielectric layer;   forming a second part of the dielectric layer over the substrate;   forming a plurality of via openings/openings in the second part of the dielectric layer to expose parts of the conductive layers; and   forming a plurality of conductive plugs in the via openings/openings so as to constitute the vias/connecting portions.   
     
     
         18 . The method of  claim 14 , wherein the first bonding pad structures extend from a edge of the die seal ring region to the scribed lines on the substrate. 
     
     
         19 . The method of  claim 14 , further comprising the steps of forming a plurality of second bonding pad structures in the internal region before performing the cutting process along the scribe lines on the substrate.