Mos-gated device having a buried gate and process for forming same

Abstract

An improved trench MOS-gated device comprises a monocrystalline semiconductor substrate on which is disposed a doped upper layer. The upper layer includes at an upper surface a plurality of heavily doped body regions having a first polarity and overlying a drain region. The upper layer further includes at its upper surface a plurality of heavily doped source regions having a second polarity opposite that of the body regions. A gate trench extends from the upper surface of the upper layer to the drain region and separates one source region from another. The trench has a floor and sidewalls comprising a layer of dielectric material and contains a conductive gate material filled to a selected level and an isolation layer of dielectric material that overlies the gate material and substantially fills the trench. The upper surface of the overlying layer of dielectric material in the trench is thus substantially coplanar with the upper surface of the upper layer. A process for forming an improved MOS-gate device provides a device whose gate trench is filled to a selected level with a conductive gate material, over which is formed an isolation dielectric layer whose upper surface is substantially coplanar with the upper surface of the upper layer of the device.

1 . A trench MOS-gated device comprising:
 a) a substrate comprising doped monocrystalline silicon semiconductor material of a first conductivity type;   b) a doped upper layer of a second conductivity type opposite to said first conductivity type disposed on said substrate having a plurality of heavily doped source regions of said second conductivity type extending from an upper surface of said upper layer to a selected depth in said upper layer; and   c) a gate trench separating one of said source regions from a second source region,   
     said trench extending from said upper surface of said upper layer to said drain region, said trench having a floor and sidewalls comprising a layer of dielectric material, and being partially filled with a conductive material to a selected level substantially below said upper surface of said upper layer with the remainder of said partially filled trench being filled with an isolation layer of dielectric material overlying and directly located on said gate material, said overlying layer of dielectric material in said trench having an upper surface that is substantially coplanar with said upper surface of said upper layer. 
   
   
       2 . A trench MOS-gated device comprising:
 a) a substrate comprising doped monocrystalline silicon semiconductor material of a first conductivity type;   b) a doped upper layer of a second conductivity type opposite to said first conductivity type disposed on said substrate;   c) a plurality of heavily doped body regions in said upper layer of said second conductivity type;   d) a plurality of heavily doped source regions extending from an upper surface of said upper layer to a selected depth in said upper layer;   e) a gate trench separating one of said source regions from a second source region,   
     said trench extending from said upper surface of said upper layer to said drain region, said trench having a floor and sidewalls comprising a layer of dielectric material, and being partially filled with a conductive material to a selected level substantially below said upper surface of said upper layer with the remainder of said partially filled trench being filled with an isolation layer of dielectric material overlying and directly located on said gate material, said overlying layer of dielectric material in said trench having an upper surface that is substantially coplanar with said upper surface of said upper layer; and
 f) said plurality of body regions and said plurality of source regions comprise a plurality of arrays of alternating body regions and source regions wherein one of said arrays is separated from a second of said arrays by said gate trench. 
 
   
   
       3 . (canceled) 
   
   
       4 . A process for forming a trench MOS-gated device, said process comprising:
 (a) forming a doped upper layer on a semiconductor substrate, said upper layer having an upper surface and an underlying drain region;   (b) forming a well region having a first polarity in said upper layer, said well region overlying said drain region;   (c) forming a gate trench mask on said upper surface of said upper layer;   (d) forming a gate trench extending from the upper surface of said upper layer through said well region to said drain region, said gate trench having sidewalls and a floor;   (e) covering said sidewalls and floors with a layer of dielectric material;   (f) forming gate electrodes in the trenches to a selected level substantially below the upper surface of said upper level with a conductive gate material substantially coplanar with the level of the conductive gate material in the trenches;   (g) removing said trench mask from the upper surface of said upper layer;   (h) forming an isolation layer of dielectric material on the upper surface of said upper layer, said isolation layer overlying said gate material;   (i) removing said isolation layer from the upper surface of said upper layer, a portion of said isolation layer remaining within and substantially filling said trench, and having an upper surface that is proximate to and slightly below the upper surface of said upper layer,   (j) forming a plurality of heavily doped source regions that extend into the substrate along the sides of the trenches;   (k) forming a plurality of heavily doped body regions having a first polarity, said body regions overlying the drain region in said upper layer; and   (l) forming a metal contact to said body and source regions over the upper surface of said upper layer.