Active regions with compatible dielectric layers
Abstract
A method to form a semiconductor structure with an active region and a compatible dielectric layer is described. In one embodiment, a semiconductor structure has a dielectric layer comprised of an oxide of a first semiconductor material, wherein a second (and compositionally different) semiconductor material is formed between the dielectric layer and the first semiconductor material. In another embodiment, a portion of the second semiconductor material is replaced with a third semiconductor material in order to impart uniaxial strain to the lattice structure of the second semiconductor material.
Claims
exact text as granted — not AI-modified1 . A semiconductor structure comprising:
a substrate comprised of a first semiconductor material; an active region above said substrate, wherein said active region is comprised of a second semiconductor material, and wherein the composition of said second semiconductor material is different from that of said first semiconductor material; and a dielectric layer directly above said active region, wherein said dielectric layer is comprised of a layer of oxide of said first semiconductor material directly above said active region.
2 . The semiconductor structure of claim 1 wherein said first semiconductor material is comprised of silicon, and wherein said layer of oxide is selected from the group consisting of a layer of silicon dioxide or silicon oxy-nitride.
3 . The semiconductor structure of claim 2 wherein the atomic concentration of silicon atoms in said first semiconductor material is greater than 97%.
4 . The semiconductor structure of claim 1 wherein said second semiconductor material is comprised of a material selected from the group consisting of gallium nitride, gallium phosphide, gallium arsenide, indium phosphide, indium antimonide, indium gallium arsenide, aluminum gallium arsenide, indium gallium phosphide, germanium or silicon/germanium with an atomic concentration of germanium atoms greater than 5%.
5 . The semiconductor structure of claim 4 wherein said first semiconductor material is comprised of silicon, and wherein said layer of oxide is selected from the group consisting of a layer of silicon dioxide or silicon oxy-nitride.
6 . The semiconductor structure of claim 1 wherein said dielectric layer further comprises a layer of a high-K dielectric material above said layer of oxide of said first semiconductor material.
7 . The semiconductor structure of claim 6 , wherein said first semiconductor material is comprised of silicon, wherein said layer of oxide is selected from the group consisting of a layer of silicon dioxide or silicon oxy-nitride, and wherein said high-K dielectric material is selected from the group consisting of hafnium oxide, hafnium silicate, lanthanum oxide, zirconium oxide, zirconium silicate, tantalum oxide, barium strontium titanate, barium titanate, strontium titanate, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, lead zinc niobate or a combination thereof.
8 . A semiconductor device comprising:
a substrate comprised of a first semiconductor material; an active region above said substrate, wherein said active region is comprised of a second semiconductor material, and wherein the composition of said second semiconductor material is different from that of said first semiconductor material; a gate dielectric layer directly above said active region, wherein said gate dielectric layer is comprised of a layer of oxide of said first semiconductor material directly above said active region; a gate electrode above said gate dielectric layer; a pair of tip extensions on either side of said gate electrode and in said active region; a pair of gate isolation spacers adjacent to the sidewalls of said gate electrode and above said pair of tip extensions; and a pair of source/drain regions on either side of said pair of gate isolation spacers and in said active region.
9 . The semiconductor device of claim 8 wherein said first semiconductor material is comprised of silicon, and wherein said layer of oxide is selected from the group consisting of a layer of silicon dioxide or silicon oxy-nitride.
10 . The semiconductor device of claim 9 wherein the atomic concentration of silicon atoms in said first semiconductor material is greater than 97%.
11 . The semiconductor device of claim 8 wherein said second semiconductor material is comprised of a material selected from the group consisting of gallium nitride, gallium phosphide, gallium arsenide, indium phosphide, indium antimonide, indium gallium arsenide, aluminum gallium arsenide, indium gallium phosphide, germanium or silicon/germanium with an atomic concentration of germanium atoms greater than 5%.
12 . The semiconductor device of claim 11 wherein said first semiconductor material is comprised of silicon, and wherein said layer of oxide is selected from the group consisting of a layer of silicon dioxide or silicon oxy-nitride.
13 . The semiconductor device of claim 8 wherein said gate dielectric layer further comprises a layer of a high-K dielectric material above said layer of oxide of said first semiconductor material.
14 . The semiconductor device of claim 13 , wherein said first semiconductor material is comprised of silicon, wherein said layer of oxide is selected from the group consisting of a layer of silicon dioxide or silicon oxy-nitride, and wherein said high-K dielectric material is selected from the group consisting of hafnium oxide, hafnium silicate, lanthanum oxide, zirconium oxide, zirconium silicate, tantalum oxide, barium strontium titanate, barium titanate, strontium titanate, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, lead zinc niobate or a combination thereof.
15 . The semiconductor device of claim 8 wherein said pair of source/drain regions is comprised of a third semiconductor material, and wherein the composition of said third semiconductor material is different from that of said second semiconductor material.
16 . A semiconductor device comprising:
a substrate comprised of a first semiconductor material; an active region above said substrate, wherein said active region is comprised of a second semiconductor material, and wherein the composition of said second semiconductor material is different from that of said first semiconductor material; a gate dielectric layer above said active region; a gate electrode above said gate dielectric layer; a pair of tip extensions on either side of said gate electrode and in said active region; a pair of gate isolation spacers adjacent to the sidewalls of said gate electrode and above said pair of tip extensions; and a pair of source/drain regions on either side of said pair of gate isolation spacers and in said active region, wherein said pair of source/drain regions is comprised of a third semiconductor material, and wherein the composition of said third semiconductor material is different from that of said second semiconductor material.
17 . The semiconductor device of claim 16 wherein the atomic concentration of silicon atoms in said first semiconductor material is greater than 97%.
18 . The semiconductor device of claim 17 wherein said second semiconductor material is comprised of a material selected from the group consisting of gallium nitride, gallium phosphide, gallium arsenide, indium phosphide, indium antimonide, indium gallium arsenide, aluminum gallium arsenide, indium gallium phosphide, germanium or silicon/germanium with an atomic concentration of germanium atoms greater than 5%.
19 . The semiconductor device of claim 16 , wherein said gate dielectric layer is comprised of a material selected from the group consisting of silicon dioxide, silicon oxy-nitride, hafnium oxide, hafnium silicate, lanthanum oxide, zirconium oxide, zirconium silicate, tantalum oxide, barium strontium titanate, barium titanate, strontium titanate, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, lead zinc niobate or a combination thereof.
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