Semiconductor memory cell and method of forming same

Abstract

A semiconductor memory cell and forming method thereof utilizes a vertical select transistor to eliminate the problem of a large cell surface area in memory cells of the related art utilizing phase changes. A memory cell with a smaller surface area than the DRAM device of the related art is achieved by the present invention. Besides low power consumption during read operation, the invention also provides phase change memory having low power consumption even during write operation. Phase change memory also has stable read-out operation.

1 . A semiconductor device comprising:
 a first insulator film;   a first wiring formed on the first insulator film and extending in a first direction;   a selection element formed above the first wiring and made of a poly-silicon;   a chalcogenide material formed above the selection element to store information;   a second wiring formed above the chalcogenide material and extending in a second direction across the first direction.   
     
     
         2 . A semiconductor device according to  claim 1 ,
 wherein the first wiring is formed after forming the first insulator film.   
     
     
         3 . A semiconductor device according to  claim 1 , further comprising:
 a second insulator film formed between the first insulator film so as to cover the first insulator film and the first wiring; and   a plug formed between the first wiring and the selection element in the second insulator film.   
     
     
         4 . A semiconductor device according to  claim 3 ,
 wherein the plug is made of a poly-silicon.   
     
     
         5 . A semiconductor device according to  claim 1 ,
 wherein the poly-silicon of the selection element has impurity layers that include a first conductivity type and a second conductivity type opposite to the first conductivity type.   
     
     
         6 . A semiconductor device according to  claim 5 ,
 wherein the impurity layers of the selection element has a first impurity layer that is the first conductivity type, a second impurity layer that is the second conductivity type, and a third impurity layer that is the first conductivity type, and   wherein the second impurity layer is formed between the first and third impurity layers.   
     
     
         7 . A semiconductor device according to  claim 6 ,
 wherein the selection element has a pillar structure that has the first to third impurity layers and a word line formed along a side of the pillar structure.   
     
     
         8 . A semiconductor device according to  claim 1 ,
 wherein a current flows between the first wiring and the second wiring through the selection element and the chalcogenide material to read/write the information from/into the chalcogenide material.   
     
     
         9 . A semiconductor device according to  claim 1 ,
 wherein the chalcogenide material contains at least tellurium.