Personalized hardware

Abstract

A system for personalizing one or more electrical circuits having plurality of layers with electrical characteristics. The layers being produced by an electrical characteristic determination process (ECDP). The system for personalizing includes a wafer stage for receiving a wafer in order to produce a plurality of electrical circuits. The system is configured to apply a personalization process during production of the layers. The personalization process includes using a first ECDP in the layer to product identical electrical characteristics on the wafer in each of the plurality of electrical circuits, and using a second ECDP in the layer to modify one or more electrical characteristics in selected electrical circuits so as to incorporate in the selected circuits an individualized digital number, giving rise to the desired personalizing of one or more of the specified electrical circuits. Related apparatus and methods are also provided.

1 . A method for personalizing an electrical circuit having at least one layer having electrical characteristics, the layer being produced by an electrical characteristic determination process (ECDP), the method for personalizing comprising:
 providing a wafer suitable for producing thereon a plurality of electrical circuits each having at least one layer; and   during production of the at least one layer;   using a first ECDP on at least one photoresist layer to produce a pattern in the at least one photoresist layer corresponding to electrical circuitry having identical electrical characteristics on the wafer in each of the plurality of electrical circuits;   using a second ECDP, including a personalization algorithm, on said at least one photoresist layer to produce a pattern therein which corresponds to a modification of at least one electrical characteristic of at least one of the plurality of electrical circuits; and   developing said at least one photoresist layer after patterning thereof to produce said plurality of electrical circuits,   said personalization algorithm being used for generating at least one of a random individualized digital number and a pseudo-random individualized digital number in each of said plurality of electrical circuits by selectively exposing said at least one photoresist layer thereby introducing said digital number.   
   
   
       2 . The method according to  claim 1  and wherein the first ECDP and the second ECDP each comprise optical lithography. 
   
   
       3 . The method according to  claim 1  and wherein the first ECDP and the second ECDP each comprise direct beam writing. 
   
   
       4 . The method according to  claim 1  and wherein the first ECDP comprises parallel optical photolithography, and the second ECDP comprises at least one of direct laser beam writing and direct e-beam writing. 
   
   
       5 . The method according to  claim 1 , wherein said at least one manufacturing parameter is selected from the group consisting of a lot number, a wafer number and an electrical circuit x-y coordinates that uniquely defines each of said plurality of electrical circuits. 
   
   
       6 . The method according to  claim 1  and also comprising:
 covering said at least one layer by at least one subsequent layer, said at least one subsequent layer including at least one of a dielectric layer and a metal layer, in order to hide said modification in each of said plurality of electrical circuits, thereby hindering reverse-engineering analysis.   
   
   
       7 . The method according to  claim 1  and also comprising utilizing planarization to hinder reverse-engineering analysis. 
   
   
       8 . The method according to  claim 1 , wherein said at least one of a random individualized digital number and a pseudo-random individualized digital number is a digital key. 
   
   
       9 . The method according to  claim 1 , wherein the modification of at least one electrical characteristic of at least one of the plurality of electrical circuits comprises modifying by exposure through at least one Personalized Secure Hardware (PSH) photo-mask. 
   
   
       10 . The method according to  claim 9 , wherein at least one of said at least one PSH photo-mask is a dedicated PSH mask. 
   
   
       11 . The method according to  claim 9 , wherein at least one of said at least one PSH photo-mask is combined with a general photomask. 
   
   
       12 . The method according to  claim 1 , wherein:
 said first ECDP comprises parallel optical photolithography;   said second ECDP comprises direct writing; and   said direct writing includes scanning the wafer in either one of X and Y directions and applying during said scanning strobe on-the-fly so as to accomplish said modification.   
   
   
       13 . The method according to  claim 12 , wherein said direct writing comprises direct laser beam writing. 
   
   
       14 . The method according to  claim 12 , wherein said direct writing comprises direct e-beam writing. 
   
   
       15 . The method according to  claim 1 , wherein said at least one of a random individualized digital number and a pseudo-random individualized digital number serves as an input to an application. 
   
   
       16 . A method for personalizing an electrical circuit having at least one layer having electrical characteristics, the layer being produced by an electrical characteristic determination process (ECDP), the method for personalizing comprising:
 providing a wafer suitable for producing thereon a plurality of electrical circuits each having at least one layer; and   during production of the at least one layer:   using a first ECDP on at least one photoresist layer to produce a pattern in the at least one photoresist layer corresponding to electrical circuitry having identical electrical characteristics on the wafer in each of the plurality of electrical circuits; and   using a second ECDP, including a personalization algorithm, on said at least one photoresist layer to produce a pattern therein which corresponds to a modification of at least one electrical characteristic of at least one of the plurality of electrical circuits, the second ECDP comprising direct writing; and   wherein said direct writing includes   scanning the wafer in either one of X and Y directions and applying during said scanning strobe on-the-fly so as to accomplish said modifications, thereby personalizing the at least one of the plurality of electrical circuits,   said personalization algorithm being used for generating at least one of a random individualized digital number and a pseudo-random individualized digital number in each of said plurality of electrical circuits by selectively exposing said at least one photoresist layer thereby introducing said digital number.   
   
   
       17 . The method according to  claim 1 , wherein each of said plurality of electrical circuits implements at least one of the following: a redundancy design; a debug design; and a chip design. 
   
   
       18 . The method according to  claim 1  wherein said using a first ECDP comprises using a photo mask for a general lithography exposure, said photo mask including pre-defined PSH link locations for personalization in an additional exposure. 
   
   
       19 . The method according to  claim 18  and wherein the general lithography comprises optical lithography. 
   
   
       20 . The method according to  claim 18  and wherein the additional exposure comprises direct write lithography.