Dual stress liner

Abstract

A semiconductor device structure is provided which includes a first field effect transistor (“FET”) having a first channel region, a first source region, a first drain region and a first gate conductor overlying the first channel region. A second FET is included which has a second channel region, a second source region, a second drain region and a second gate conductor overlying the second channel region. The first and second gate conductors are portions of a single elongated conductive member extending over both the first and second channel regions. A first stressed film overlies the first FET, the first stressed film applying a stress having a first value to the first channel region. A second stressed film overlies the second FET, the second stressed film applying a stress having a second value to the second channel region. The second value is substantially different from the first value. In addition, the first and second stressed films abut each other at a common boundary and present a substantially co-planar major surface at the common boundary.

1 . A semiconductor device structure, comprising: 
 a first field effect transistor (“FET”) having a first channel region, a first source region, a first drain region and a first gate conductor overlying said first channel region;    a second FET having a second channel region, a second source region, a second drain region and a second gate conductor overlying said second channel region, said first and second gate conductors being portions of a single elongated conductive member extending over both said first and second channel regions;    a first stressed film overlying said first FET, said first stressed film applying a stress having a first value to said first channel region; and    a second stressed film overlying said second FET, said second stressed film applying a stress having a second value to said second channel region, said second value being substantially different from said first value,    wherein said first and second stressed films abut each other at a common boundary and present a substantially co-planar major surface at said common boundary.    
   
   
       2 . The semiconductor device structure as claimed in  claim 1 , wherein neither one of said first and second stressed films overlaps the other one of said first and second stressed films at said common boundary.  
   
   
       3 . The semiconductor device structure as claimed in  claim 2 , further comprising an interlevel dielectric layer (“ILD”) overlying said first and second stressed films, said conductive via extending through said ILD and said first and second stressed films at said common boundary to contact said conducting member.  
   
   
       4 . The semiconductor device structure as claimed in  claim 2 , wherein said first value is compressive and said second value is tensile.  
   
   
       5 . The semiconductor device structure as claimed in  claim 4 , wherein said first FET includes a PFET and said second FET includes an NFET.  
   
   
       6 . The semiconductor device structure as claimed in  claim 2 , wherein said first source region, first channel region and first drain region of said first FET are provided in a first semiconductor region, said second source region, second channel region and second drain region are provided in a second semiconductor region, said semiconductor device structure further comprising at least one isolation region separating and electrically isolating said first and second semiconductor regions.  
   
   
       7 . The semiconductor device structure as claimed in  claim 2 , wherein major surfaces of said first and second stressed films are at least substantially planar.  
   
   
       8 . The semiconductor device structure as claimed in  claim 2 , wherein said first and second gate conductors include top surfaces remote from said first and second channel regions, respectively, and said first and second stressed films overlie said top surfaces of said first and second gate conductors.  
   
   
       9 . The semiconductor device structure as claimed in  claim 2 , wherein said first stressed film and said second stressed film each consist of nitride.  
   
   
       10 . The semiconductor device structure as claimed in  claim 9 , wherein said first and said second semiconductor regions consist essentially of silicon and said nitride includes silicon nitride.