High performance system-on-chip using post passivation process

Abstract

The present invention extends the above referenced continuation-in-part application by in addition creating high quality electrical components, such as inductors, capacitors or resistors, on a layer of passivation or on the surface of a thick layer of polymer. In addition, the process of the invention provides a method for mounting discrete electrical components at a significant distance removed from the underlying silicon surface.

1 . An integrated circuit chip comprising: 
 a silicon substrate;    multiple semiconductor devices in or on said silicon substrate, wherein one of said multiple semiconductor devices comprises a transistor;    a first dielectric layer over said silicon substrate;    a first metallization structure over said first dielectric layer, wherein said first metallization structure is connected to said multiple semiconductor devices, wherein said first metallization structure comprises a first metal layer and a second metal layer over said first metal layer, and wherein said first metallization structure comprises electroplated copper;    a second dielectric layer between said first and second metal layers;    a passivation layer over said first metallization structure and over said first and second dielectric layers, wherein said passivation layer comprises a topmost oxide layer of said integrated circuit chip and a topmost nitride layer of said integrated circuit chip, wherein said topmost nitride layer is over said topmost oxide layer, and wherein a first opening in said passivation layer exposes a pad of said first metallization structure, wherein said first opening has a transverse dimension between 0.5 and 30 micrometers;    a polymer layer over said passivation layer, wherein a second opening in said polymer layer exposes said pad, and wherein said polymer layer has a thickness between 2 and 150 micrometers; and    a second metallization structure comprising a first portion in said second opening and a second portion on said polymer layer, wherein said first and second portions comprise electroplated copper, and wherein said second portion has a thickness greater than those of said first and second metal layers.    
   
   
       2 . The integrated circuit chip of  claim 1 , wherein said polymer layer comprises polyimide.  
   
   
       3 . The integrated circuit chip of  claim 1 , wherein said polymer layer comprises benzocyclobutene (BCB).  
   
   
       4 . The integrated circuit chip of  claim 1 , wherein said topmost nitride layer has a thickness greater than that of said topmost oxide layer.  
   
   
       5 . The integrated circuit chip of  claim 1 , wherein said polymer layer has a thickness greater than that of said passivation layer.  
   
   
       6 . An integrated circuit chip comprising: 
 a silicon substrate;    multiple semiconductor devices in or on said silicon substrate, wherein one of said multiple semiconductor devices comprises a transistor;    a first dielectric layer over said silicon substrate;    a first metallization structure over said first dielectric layer, wherein said first metallization structure is connected to said multiple semiconductor devices, wherein said first metallization structure comprises a first metal layer and a second metal layer over said first metal layer, and wherein said first metallization structure comprises electroplated copper;    a second dielectric layer between said first and second metal layers;    a passivation layer over said first metallization structure and over said first and second dielectric layers, wherein said passivation layer comprises a topmost oxide layer of said integrated circuit chip and a topmost nitride layer of said integrated circuit chip, wherein said topmost nitride layer is over said topmost oxide layer, and wherein a first opening in said passivation layer exposes a pad of said first metallization structure, wherein said first opening has a transverse dimension between 0.5 and 30 micrometers;    a polymer layer over said passivation layer, wherein a second opening in said polymer layer exposes said pad, wherein said second opening has a transverse dimension between 0.5 and 30 micrometers, and wherein said polymer layer has a thickness between 2 and 150 micrometers; and    a second metallization structure comprising a first portion in said second opening and a second portion on said polymer layer, wherein said first and second portions comprise electroplated copper, and wherein said second portion has a thickness greater than those of said first and second metal layers.    
   
   
       7 . The integrated circuit chip of  claim 6 , wherein said polymer layer comprises polyimide.  
   
   
       8 . The integrated circuit chip of  claim 6 , wherein said polymer layer comprises benzocyclobutene (BCB).  
   
   
       9 . The integrated circuit chip of  claim 6 , wherein said topmost nitride layer has a thickness greater than that of said topmost oxide layer.  
   
   
       10 . The integrated circuit chip of  claim 6 , wherein said polymer layer has a thickness greater than that of said passivation layer.  
   
   
       11 . An integrated circuit chip comprising: 
 a silicon substrate;    multiple semiconductor devices in or on said silicon substrate, wherein one of said multiple semiconductor devices comprises a transistor;    a first dielectric layer over said silicon substrate;    a first metallization structure over said first dielectric layer, wherein said first metallization structure is connected to said multiple semiconductor devices, wherein said first metallization structure comprises a first metal layer and a second metal layer over said first metal layer, wherein said first metallization structure comprises a pad, wherein said pad has a size between 0.5 and 30 micrometers, and wherein said first metallization structure comprises electroplated copper;    a second dielectric layer between said first and second metal layers;    a passivation layer over said first metallization structure and over said first and second dielectric layers, wherein said passivation layer comprises a topmost oxide layer of said integrated circuit chip and a topmost nitride layer of said integrated circuit chip, wherein said topmost nitride layer is over said topmost oxide layer, and wherein a first opening in said passivation layer exposes said pad, wherein said first opening has a transverse dimension between 0.5 and 30 micrometers;    a polymer layer over said passivation layer, wherein a second opening in said polymer layer exposes said pad, and wherein said polymer layer has a thickness between 2 and 150 micrometers; and    a second metallization structure comprising a first portion in said second opening and a second portion on said polymer layer, wherein said first and second portions comprise electroplated copper, and wherein said second portion has a thickness greater than those of said first and second metal layers.    
   
   
       12 . The integrated circuit chip of  claim 11 , wherein said polymer layer comprises polyimide.  
   
   
       13 . The integrated circuit chip of  claim 11 , wherein said polymer layer comprises benzocyclobutene (BCB).  
   
   
       14 . The integrated circuit chip of  claim 11 , wherein said topmost nitride layer has a thickness greater than that of said topmost oxide layer.  
   
   
       15 . The integrated circuit chip of  claim 11 , wherein said polymer layer has a thickness greater than that of said passivation layer.