Asymmetric multi-gated transistor and method for forming

Abstract

In one embodiment, there is an asymmetric multi-gated transistor that has a semiconductor fin with a non-uniform doping profile. A first portion of the fin has a higher doping concentration while a second portion of the fin has a lower doping concentration. In another embodiment, there is an asymmetric multi-gated transistor with gate dielectrics formed on the semiconductor fin that vary in thickness. This asymmetric multi-gated transistor has a thin gate dielectric formed on a first side portion of the semiconductor fin and a thick gate dielectric formed on a second side portion of the fin.

1 . An asymmetric multi-gated transistor, comprising:
 a substrate;   a semiconductor fin formed on the substrate, wherein the semiconductor fin is asymmetrically doped with a semiconductor dopant, wherein a first side portion of the fin has a high doping concentration and a second side portion opposite therefrom has a lower doping concentration;   a gate dielectric formed on the fin, wherein the gate dielectric comprises a first gate dielectric formed on the first side portion of the fin having a high doping concentration and a second gate dielectric formed on the second side portion of the fin having a lower doping concentration;   a first gate conductor formed on the first gate dielectric; and   a second gate conductor formed on the second gate dielectric.   
   
   
       2 . The transistor according to  claim 1 , wherein the semiconductor dopant comprises a dopant selected from the group consisting of hydrogen (H), deuterium (D), nitrogen (N), helium (He), neon (Ne), argon (Ar), krypton (Kr), xenon (Xe), carbon (C), oxygen ( 0 ), fluorine (F), phosphorus (P), arsenic (As), antimony (Sb), boron (B), indium (In), and thallium (TI). 
   
   
       3 . The transistor according to  claim 1 , wherein the side portion of the fin with a high doping concentration has a higher threshold voltage when controlled by the first gate conductor and the portion of the fin with a lower doping concentration has a lower threshold voltage when controlled by the second gate conductor. 
   
   
       4 . The transistor according to  claim 1 , wherein the first gate dielectric formed on the first side portion of the fin has a thickness substantially the same as the thickness of the second gate dielectric formed on the side portion of the fin having a lower doping concentration. 
   
   
       5 . The transistor according to  claim 1 , wherein the first gate dielectric formed on the first side portion of the fin has a thickness that differs from the thickness of the second gate dielectric formed on the side portion of the fin having a lower doping concentration. 
   
   
       6 . The transistor according to  claim 1 , wherein the semiconductor fin further comprises a top portion asymmetrically doped with the semiconductor dopant, wherein the top portion has a high doping concentration. 
   
   
       7 . The transistor according to  claim 6 , wherein the gate dielectric further comprises a third gate dielectric formed on the top portion of the fin having a high doping concentration. 
   
   
       8 . The transistor according to  claim 7 , further comprising a third gate conductor formed on the third gate dielectric, wherein the third gate dielectric has a thickness that is substantially the same as one of the first gate dielectric and second gate dielectric. 
   
   
       9 . An integrated circuit on a semiconductor on insulator chip comprising the transistor of  claim 1 . 
   
   
       10 . A method for forming an asymmetric multi-gated transistor, comprising:
 forming a semiconductor fin on a substrate;   asymmetrically doping the semiconductor fin with a semiconductor dopant, wherein the asymmetrically doping comprises doping a first side portion of the fin with a high doping concentration of dopant and doping a second side portion of the fin with a lower doping concentration;   forming a gate dielectric on the fin, wherein the forming of the gate dielectric comprises forming a first gate dielectric on the first side portion of the fin having the high doping concentration and forming a second gate dielectric on the second portion of the fin having the lower doping concentration;   forming a first gate conductor on the first gate dielectric; and   forming a second gate conductor on the second gate dielectric.   
   
   
       11 . The method according to  claim 10 , wherein the semiconductor dopant comprises a dopant selected from the group consisting of hydrogen (H), deuterium (D), nitrogen (N), helium (He), neon (Ne), argon (Ar), krypton (Kr), xenon (Xe), carbon (C), oxygen ( 0 ), fluorine (F), phosphorus (P), arsenic (As), antimony (Sb), boron (B), indium (In), and thallium (TI). 
   
   
       12 . The method according to  claim 10 , further comprising forming a capping layer above the semiconductor fin. 
   
   
       13 . The method according to  claim 10 , further comprising asymmetrically doping a top portion of the semiconductor fin with the semiconductor dopant, wherein the top portion has a high doping concentration 
   
   
       14 . The method according to  claim 13 , wherein the forming of the gate dielectric comprises forming a third gate dielectric on the top portion of the fin and the forming of the gate conductor comprises forming a third gate conductor on the third gate dielectric. 
   
   
       15 . A method for forming an asymmetric multi-gated transistor, comprising:
 forming a semiconductor fin on a substrate;   incorporating a first side portion of the semiconductor fin with an implant material;   growing a gate dielectric on the semiconductor fin, wherein the first side portion of the semiconductor fin with the implant material grows a first gate dielectric with a thickness that differs from a thickness of a second gate dielectric that grows on a second side portion of the semiconductor fin;   forming a first gate conductor on the first gate dielectric; and   forming a second gate conductor on the second gate dielectric.   
   
   
       16 . The method according to  claim 15 , wherein the implant material in the semiconductor fin determines a difference in thickness between the first gate dielectric and the second gate dielectric. 
   
   
       17 . The method according to  claim 15 , further comprising forming a capping layer above the semiconductor fin, wherein the capping layer covers a top portion of each of the first gate dielectric, semiconductor fin and the second gate dielectric. 
   
   
       18 . The method according to  claim 15 , further comprising incorporating a top portion of the semiconductor fin with the implant material. 
   
   
       19 . The method according to  claim 18 , wherein the growing of the gate dielectric comprises growing a third gate dielectric on the top portion of the fin, wherein the third gate dielectric has a thickness that is substantially the same as one of the first gate dielectric and second gate dielectric. 
   
   
       20 . The method according to  claim 19 , further comprising forming a third gate conductor on the third gate dielectric.