Self Terminating Overburden Free Plating (STOP) Of Metals On Patterned Wafers

Abstract

A method of performing electrochemical deposition is provided to minimize overburden. A constant plating voltage (and a variable plating current) is applied across a semiconductor structure (e.g., patterned dielectric layer) and a metal electrode, which are both submerged in an electrolyte that contains both suppressor and accelerator molecules. The constant plating voltage is selected such that the suppressor molecules are predominantly active on the flat upper surface of the patterned dielectric layer, and the accelerator molecules are predominantly active within the patterned features of the patterned dielectric layer. As a result, metal is deposited at a relatively high rate within the patterned features, and at a relatively low rate on the flat upper surface areas of the patterned dielectric layer. Consequently, the patterned features are filled with metal before significant overburden can be formed over the flat upper surface areas of the patterned dielectric layer.

1 . An electrochemical deposition method comprising:
 immersing a semiconductor structure in a plating solution containing an accelerator and a suppressor, wherein the semiconductor structure includes an upper surface having one or more flat regions and one or more patterned features;   immersing a metal electrode in the plating solution; and   applying a plating voltage across the semiconductor structure and the metal electrode, wherein the plating voltage is selected such that metal is deposited in the one or more patterned features at a first rate, and deposited on the one or more flat regions at a second rate, wherein the first rate is substantially greater than the second rate.   
     
     
         2 . The method of  claim 1 , further comprising selecting the plating voltage such that the first rate is at least about 10 times greater than the second rate. 
     
     
         3 . The method of  claim 1 , wherein the plating voltage is constant. 
     
     
         4 . The method of  claim 1 , wherein the plating voltage is applied by grounding the semiconductor structure and applying a negative voltage to the metal electrode. 
     
     
         5 . The method of  claim 1 , wherein the negative voltage is greater than or equal to about −0.2 Volts. 
     
     
         6 . The method of  claim 1 , wherein the metal electrode comprises copper. 
     
     
         7 . The method of  claim 1 , wherein the plating solution comprises sulfuric acid and copper. 
     
     
         8 . The method of  claim 1 , wherein the semiconductor structure comprises a wafer and a patterned dielectric layer, wherein the patterned features are located in the patterned dielectric layer. 
     
     
         9 . The method of  claim 1 , wherein the one or more patterned features have an aspect ratio greater than three. 
     
     
         10 . The method of  claim 1 , wherein the one or more patterned features are concave. 
     
     
         11 . The method of  claim 1 , wherein the plating voltage is selected to maximize the difference between the first rate and the second rate.