Multi-layer nonvolatile memory devices and methods of fabricating the same

Abstract

A nonvolatile memory device includes a semiconductor substrate having a first well region of a first conductivity type, and at least one semiconductor layer formed on the semiconductor substrate. A first cell array is formed on the semiconductor substrate, and a second cell array formed on the semiconductor layer. The semiconductor layer includes a second well region of the first conductivity type having a doping concentration greater than a doping concentration of the first well region of the first conductivity type. As the doping concentration of the second well region is increased, a resistance difference may be reduced between the first and second well regions.

1 . A nonvolatile memory device, comprising:
 a semiconductor substrate having a first well region of a first conductivity type;   at least one semiconductor layer formed on the semiconductor substrate;   a first cell array formed on the semiconductor substrate; and   a second cell array formed on the semiconductor layer;   wherein the semiconductor layer includes a second well region of the first conductivity type having a concentration greater than a concentration of the first well region of the first conductivity type.   
     
     
         2 . The nonvolatile memory device of  claim 1 , wherein the semiconductor layer comprises:
 a first semiconductor layer; and   a second semiconductor layer on the first semiconductor layer;   wherein the second well region is formed in the first semiconductor layer, and a third well region of the first conductivity type having a doping concentration equal to or less than that of the second well region is formed in the second semiconductor layer.   
     
     
         3 . The nonvolatile memory device of  claim 2 , wherein the doping concentration of the third well region is approximately equal to the doping concentration of the first well region. 
     
     
         4 . The nonvolatile memory device of  claim 2 , further comprising a second conductivity type well formed in a lower portion of the first semiconductor layer,;
 wherein the second well region is formed on the second conductivity type well in the first semiconductor layer.   
     
     
         5 . The nonvolatile memory device of  claim 4 , wherein a plurality of second well regions are formed in the first semiconductor layer; and
 the second conductivity type well is formed under the second well regions and between the second well regions to isolate the second well regions from each other.   
     
     
         6 . The nonvolatile memory device of  claim 2 , further comprising a device isolation layer formed in the second semiconductor layer to define an active region;
 wherein a border of the third well region is defined by the device isolation layer.   
     
     
         7 . The nonvolatile memory device of  claim 6 , wherein a bottom surface of the device isolation layer contacts a top surface of the first semiconductor layer. 
     
     
         8 . The nonvolatile memory device of  claim 6 , wherein the second well region is aligned with the device isolation layer and formed in the first semiconductor layer under the active region. 
     
     
         9 . The nonvolatile memory device of  claim 2 , wherein a thickness of the first semiconductor layer is less than a thickness of the second semiconductor layer. 
     
     
         10 . The nonvolatile memory device of  claim 9 , wherein a depth of the first well region is greater than a thickness of the semiconductor layer. 
     
     
         11 . The nonvolatile memory device of  claim 1 , wherein a depth of the first well region is greater than a depth of the second well region. 
     
     
         12 . The nonvolatile memory device of  claim 1 , wherein the first and second cell arrays comprise NAND type nonvolatile memory cells. 
     
     
         13 . A nonvolatile memory device, comprising:
 a semiconductor substrate having a first well region of a first conductivity type;   at least one semiconductor layer formed on the semiconductor substrate and having a second well region of a first conductivity type of which a concentration is higher than a concentration of the first well region of the first conductivity type;   a first device isolation layer formed on the semiconductor substrate to define a plurality of first active regions;   a second device isolation layer formed on the semiconductor layer to define a plurality of second active regions; and   a ground select line, a string select line, and word lines disposed on each of the semiconductor substrate and the semiconductor layer such that they cross over the first active regions and/or the second active regions.   
     
     
         14 . The nonvolatile memory device of  claim 13 , further comprising:
 an interlayer insulating layer interposed between the semiconductor layer and the semiconductor substrate; and   a semiconductor plug that penetrates the interlayer insulating layer;   wherein the semiconductor layer is crystal grown from the semiconductor plug.   
     
     
         15 . The nonvolatile memory device of  claim 13 , wherein a depth of the first well region is greater than a depth of the second well region. 
     
     
         16 . The nonvolatile memory device of  claim 13 , wherein the second well region formed in the semiconductor layer is disposed lower than the second device isolation layer and
 a third well region of the first conductivity type having a doping concentration less than that of the second well region is formed in the semiconductor layer over the second well region.   
     
     
         17 . The nonvolatile memory device of  claim 13 , further comprising a second conductivity type well region formed under the second well region in the semiconductor layer. 
     
     
         18 . The nonvolatile memory device of  claim 16 , wherein the third well region is formed between the second device isolation layers in the semiconductor layer and a border of the third well region is defined by the second device isolation layers. 
     
     
         19 . The nonvolatile memory device of  claim 16 , wherein the semiconductor layer comprises a first semiconductor layer and a second semiconductor layer on the first semiconductor layer;
 wherein the second well region is formed in the first semiconductor layer, and the third well region is formed in the second semiconductor layer.   
     
     
         20 . The nonvolatile memory device of  claim 19 , further comprising a second conductivity type well formed under the second well region in the first semiconductor layer. 
     
     
         21 . The nonvolatile memory device of  claim 20 , wherein a plurality of second well regions are formed in the first semiconductor layer, and the second conductivity type well is formed under the second well regions and interposed between the second well regions to isolate the second well regions from each other. 
     
     
         22 . A method of fabricating a nonvolatile memory device, the method comprising:
 forming a first well region of a first conductivity type in a semiconductor substrate;   forming an interlayer insulating layer on the semiconductor substrate;   forming a semiconductor layer on the interlayer insulating layer; and   forming a second well region of the first conductivity type in the semiconductor layer;   wherein a doping concentration of the second well region is greater than a doping concentration of the first well region.   
     
     
         23 . The method of  claim 22 , wherein a thickness of the semiconductor layer is less than a depth of the first well region. 
     
     
         24 . The method of  claim 22 , wherein forming of the semiconductor layer comprises:
 forming a first semiconductor layer on the interlayer insulating layer; and   forming a second semiconductor layer on the first semiconductor layer;   wherein the second well region is formed in the first semiconductor layer.   
     
     
         25 . The method of  claim 24 , further comprising forming a third well region of the first conductivity type in the second semiconductor layer. 
     
     
         26 . The method of  claim 25 , wherein a doping concentration of the third well region is equal to or less than a doping concentration of the second well region. 
     
     
         27 . The method of  claim 24 , wherein a plurality of the second well regions are formed in the first semiconductor layer, the second well regions are separated from each other by the second conductivity type well. 
     
     
         28 . The method of  claim 27 , wherein a plurality of second well regions are formed in the first semiconductor layer and are isolated from each other by the second conductivity type well region. 
     
     
         29 . The method of  claim 24 , wherein forming the second semiconductor layer comprises forming a mold pattern having an opening to define an active region in the first semiconductor layer;
 wherein the semiconductor layer substantially fills the opening.   
     
     
         30 . The method of  claim 24 , further comprising:
 patterning the second semiconductor layer to form a trench region defining an active region; and   filling the trench region with an insulating layer to form a device isolation layer.