Multi-Layer Electrode and Method of Forming the Same

Abstract

An interconnect includes an opening formed in a dielectric layer. A conductive barrier is deposited in the opening, over which a first conductive layer is deposited. A conductive oxide is deposited over the first conductive layer, and a second conductive layer, formed from the same material as the first conductive layer, is deposited over the conductive liner.

1 . A method of fabricating an electrode, the method comprising: 
 depositing a conductive barrier layer over a substrate;    depositing a first platinum layer over the conductive barrier layer;    depositing a conductive liner over the first platinum layer; and    depositing a second platinum layer over the conductive liner.    
   
   
       2 . The method according to  claim 1 , wherein the conductive liner comprises a conductive oxide.  
   
   
       3 . The method according to  claim 2 , wherein the conductive liner comprises iridium oxide.  
   
   
       4 . The method according to  claim 2 , wherein the conductive liner comprises ruthenium oxide.  
   
   
       5 . The method according to  claim 2 , wherein the conductive oxide is about 20-50 Angstroms thick.  
   
   
       6 . The method according to  claim 1 , wherein the first platinum layer is about 200-500 Angstroms thick.  
   
   
       7 . The method according to  claim 1 , wherein the conductive barrier layer comprises TaSiN.  
   
   
       8 . The method according to  claim 1 , wherein fabricating an electrode further comprises forming an electrode of a capacitor that is a capacitor in a DRAM cell or an FRAM cell.  
   
   
       9 . A method of forming an interconnect, the method comprising: 
 forming an opening in a dielectric layer;    depositing a conductive barrier layer in the opening;    depositing a first conductive layer over the conductive barrier layer;    depositing a conductive liner over the first conductive layer, wherein the conductive liner comprises a conductive oxide; and    depositing a second conductive layer over the conductive liner, wherein the first conductive layer and the second conductive layer comprise the same material, and wherein the second conductive layer extends below a major surface of the dielectric layer.    
   
   
       10 . The method according to  claim 9 , wherein the conductive liner comprises iridium oxide.  
   
   
       11 . The method according to  claim 9 , wherein the conductive liner comprises ruthenium oxide.  
   
   
       12 . The method according to  claim 9 , wherein the conductive liner is about 20-50 Angstroms thick.  
   
   
       13 . The method according to  claim 9 , wherein the first conductive layer is about 200-500 Angstroms thick.  
   
   
       14 . The method according to  claim 9 , wherein the conductive barrier layer comprises TaSiN.  
   
   
       15 . The method according to  claim 9 , wherein the first conductive layer and the second conductive layer comprise platinum (Pt), iridium (Ir), ruthenium (Ru), or palladium (Pd).  
   
   
       16 . The method according to  claim 9 , wherein the conductive barrier layer is formed over polysilicon formed in the opening.  
   
   
       17 . A method of forming a capacitor, the method comprising: 
 forming a TaSiN layer;    forming a first Pt layer overlying the TaSiN layer;    forming a conductive liner overlying the first Pt layer, the conductive liner comprising a material selected from the group consisting of IrO 2  and RuO 2 ;    forming a second Pt layer overlying the conductive liner;    forming a dielectric liner overlying the second Pt layer; and    forming a conductive electrode overlying the dielectric liner.    
   
   
       18 . The method of  claim 17 , wherein the capacitor comprises a capacitor of a DRAM cell.  
   
   
       19 . The method of  claim 17 , wherein the conductive liner is about 20-50 Angstroms thick and the first Pt layer is about 200-500 Angstroms thick.  
   
   
       20 . A method of forming an interconnect structure, the method comprising: 
 providing a dielectric layer;    forming an opening in the dielectric layer;    forming a barrier liner along a surface of the opening;    forming a first conductive layer over the barrier liner;    forming a conductive liner over the first conductive layer; and    forming a second conductive layer over the conductive liner, wherein the first conductive layer and the second conductive layer comprise a first material, and wherein the first material comprises platinum (Pt), iridium (Ir), ruthenium (Ru), or palladium (Pd).    
   
   
       21 . The method according to  claim 20 , wherein the conductive liner is about 20-50 Angstroms thick.  
   
   
       22 . The method according to  claim 20 , wherein the first conductive layer is about 200-500 Angstroms thick.  
   
   
       23 . The method according to  claim 20 , wherein the barrier liner comprises TaSiN.  
   
   
       24 . The method according to  claim 20 , wherein the conductive liner comprises a conductive oxide.  
   
   
       25 . The method according to  claim 20 , wherein the conductive liner comprises iridium oxide.  
   
   
       26 . The method according to  claim 20 , wherein the conductive liner comprises ruthenium oxide.  
   
   
       27 . A method of forming semiconductor device, the method comprising: 
 forming a polysilicon layer over a semiconductor body;    forming a dielectric layer over the polysilicon layer;    forming an opening in the dielectric layer, wherein at least a portion of the polysilicon layer is exposed;    depositing a conductive barrier layer over the opening, wherein the conductive barrier layer is formed over at least a portion of the exposed polysilicon;    depositing a first conductive layer over the conductive barrier layer;    depositing a conductive liner over the first conductive layer; and    depositing a second conductive layer over the conductive liner, wherein the first conductive layer and the second conductive layer comprise the same material, wherein the second conductive layer extends below a major surface of the dielectric layer, and wherein a grain structure of the first and second conductive layers is interrupted by the conductive liner.    
   
   
       28 . The method according to  claim 27 , wherein the conductive liner comprises a conductive oxide.  
   
   
       29 . The method according to  claim 28 , wherein the conductive liner comprises iridium oxide.  
   
   
       30 . The method according to  claim 28 , wherein the conductive liner comprises ruthenium oxide.  
   
   
       31 . The method according to  claim 27 , wherein the conductive liner is about 20-50 Angstroms thick.  
   
   
       32 . The method according to  claim 27 , wherein the first conductive layer is about 200-500 Angstroms thick.  
   
   
       33 . The method according to  claim 27 , wherein the conductive barrier layer comprises TaSiN.  
   
   
       34 . The method according to  claim 27 , wherein the first conductive layer and the second conductive layer comprise platinum (Pt), iridium (Ir), ruthenium (Ru), or palladium (Pd).