Delay circuit of semiconductor device

Abstract

A delay circuit of a semiconductor device increases its delay time as an external voltage increases. The delay circuit can also ensure a desired delay time according to an external voltage, without additional delay circuits. The delay circuit of the semiconductor device includes a first delay unit, and a second delay. The second delay unit has a propagation delay characteristic different from that of the first delay unit with respect to variation of a power supply voltage, wherein the first delay unit is supplied with a first power supply voltage independent of variation of an external voltage, and the second delay unit is supplied with a second power supply voltage dependent on the variation of the external voltage.

1 . A delay circuit of a semiconductor device, comprising:
 a first delay unit; and   a second delay unit having a propagation delay characteristic different from that of the first delay unit with respect to variation of a power supply voltage,   wherein the first delay unit is supplied with a first power supply voltage independent of variation of an external voltage, and the second delay unit is supplied with a second power supply voltage dependent on the variation of the external voltage.   
   
   
       2 . The delay circuit as recited in  claim 1 , further comprising a third delay unit connected between the first delay unit and the second delay unit. 
   
   
       3 . The delay circuit as recited in  claim 1 , wherein the first delay unit has a fixed delay time. 
   
   
       4 . The delay circuit as recited in  claim 1 , wherein the second delay unit has a delay time corresponding to the second power supply voltage. 
   
   
       5 . The delay circuit as recited in  claim 1 , wherein the second delay unit propagation delay characteristic includes a delay time which increases as the second power supply voltage increases. 
   
   
       6 . The delay circuit as recited in  claim 5 , wherein the second delay unit includes a MOS type capacitor. 
   
   
       7 . The delay circuit as recited in  claim 6 , wherein the MOS type capacitor includes a PMOS transistor having a source and a drain receiving the second power supply voltage, and a gate connected to an output node of the first delay unit. 
   
   
       8 . The delay circuit as recited in  claim 7 , wherein the second power supply voltage is applied to a bulk terminal of the PMOS transistor. 
   
   
       9 . The delay circuit as recited in  claim 6 , wherein the MOS type capacitor includes an NMOS transistor having a gate receiving the second power supply voltage, and a source and a drain connected to an output node of the first delay unit. 
   
   
       10 . The delay circuit as recited in  claim 9 , wherein a bulk terminal of the NMOS transistor is connected to the output node of the first delay unit. 
   
   
       11 . The delay circuit as recited in  claim 1 , wherein the second power supply voltage has a voltage level substantially equal to the external voltage. 
   
   
       12 . The delay circuit as recited in  claim 1 , wherein the first power supply voltage is supplied to the first delay unit constantly. 
   
   
       13 . A delay circuit of a semiconductor device, comprising:
 a plurality of inverters configured to receive first and second voltages independent of variation of an external voltage; and   a plurality of delay units configured to receive a third voltage dependent on the variation of the external voltage.   
   
   
       14 . The delay circuit as recited in  claim 13 , further comprising a resistor connected between the inverters and the delay units. 
   
   
       15 . The delay circuit as recited in  claim 13 , wherein the inverters have a fixed delay time. 
   
   
       16 . The delay circuit as recited in  claim 13 , wherein the delay units have a delay time corresponding to the third voltage. 
   
   
       17 . The delay circuit as recited in  claim 13 , wherein the delay units have a propagation delay characteristic in which a delay time increases as the third voltage increases. 
   
   
       18 . The delay circuit as recited in  claim 17 , wherein the delay units include a MOS type capacitor. 
   
   
       19 . The delay circuit as recited in  claim 18 , wherein the MOS type capacitor includes a PMOS transistor having a source and a drain receiving the third voltage, and a gate connected to an output node of one of the inverters. 
   
   
       20 . The delay circuit as recited in  claim 19 , wherein the third voltage is applied to a bulk terminal of the PMOS transistor. 
   
   
       21 . The delay circuit as recited in  claim 18 , wherein the MOS type capacitor includes an NMOS transistor having a gate receiving the third voltage, and a source and a drain connected to an output node of one of the inverters. 
   
   
       22 . The delay circuit as recited in  claim 21 , wherein a bulk terminal of the NMOS transistor is connected to the output node of one of the inverters. 
   
   
       23 . The delay circuit as recited in  claim 13 , wherein the third voltage has a voltage level substantially equal to the external voltage. 
   
   
       24 . The delay circuit as recited in  claim 13 , wherein the first voltage makes a power supply voltage of the inverters constant. 
   
   
       25 . The delay circuit as recited in  claim 13 , wherein the second voltage is a ground voltage.