Non-volatile memory device having separate charge trap patterns and method of fabricating the same

Abstract

A non-volatile memory device prevents charge spreading. The non-volatile memory device includes an isolation trench in a semiconductor substrate, an isolation layer partially filling the isolation trench between first and second fins defined by the isolation trench, a control gate electrode crossing the first and second fins, a first charge trap pattern between the first fin and the control gate electrode, and a second charge trap pattern between the second fin and the control gate electrode.

1 . A non-volatile memory device, comprising:
 an isolation trench in a semiconductor substrate;   an isolation layer partially filling the isolation trench between first and second fins defined by the isolation trench;   a control gate electrode crossing the first and second fins;   a first charge trap pattern between the first fin and the control gate electrode; and   a second charge trap pattern between the second fin and the control gate electrode.   
     
     
         2 . The device as claimed in  claim 1 , wherein the first and second charge trap patterns are each an insulating layer. 
     
     
         3 . The device as claimed in  claim 2 , wherein the first and second charge trap patterns are each a nitride layer. 
     
     
         4 . The device as claimed in  claim 1 , wherein the first and second charge trap patterns cover parts of the first and second fins projecting from the isolation layer. 
     
     
         5 . The device as claimed in  claim 1 , wherein a distance between the first and second charge trap patterns is smaller than a resolution limit of a photolithography process. 
     
     
         6 . The device as claimed in  claim 1 , further comprising a tunnel dielectric layer between the first and second charge trap patterns, and the first and second fins. 
     
     
         7 . The device as claimed in  claim 1 , wherein the control gate electrode covers parts of the first and second fins projecting from the isolation layer. 
     
     
         8 . The device as claimed in  claim 1 , further comprising a control dielectric layer at a lower part of the control gate electrode. 
     
     
         9 . The device as claimed in  claim 8 , wherein the control dielectric layer is between the first and second charge trap patterns and the control gate electrode, and the control dielectric layer extends to be in contact with the isolation layer between the first and second charge trap patterns. 
     
     
         10 . A method of fabricating a non-volatile memory device, comprising:
 forming an isolation trench in a semiconductor substrate, the isolation trench defining first and second fins;   forming an isolation layer partially filling the isolation trench;   forming first and second charge trap patterns respectively covering parts of the first and second fins projecting from the isolation layer; and   forming a control gate electrode covering the first and second charge trap patterns and crossing the first and second fins.   
     
     
         11 . The method as claimed in  claim 10 , wherein the charge trap patterns are each an insulating layer. 
     
     
         12 . The method as claimed in  claim 10 , wherein the charge trap patterns are each a nitride layer. 
     
     
         13 . The method as claimed in  claim 10 , wherein forming the first and second charge trap patterns comprises:
 forming a charge trap layer along a surface of the isolation layer and surfaces of the fins projecting from the isolation layer;   forming sacrificial patterns covering the charge trap layer on the fins and exposing the charge trap layer on the isolation layer; and   removing the exposed charge trap layer.   
     
     
         14 . The method as claimed in  claim 13 , wherein the sacrificial patterns are formed of a material having an etch selectivity with respect to the charge trap layer. 
     
     
         15 . The method as claimed in  claim 13 , wherein forming the sacrificial patterns comprises:
 forming a sacrificial layer on the charge trap layer;   forming a capping pattern partially filling a gap between the first and second fins, the sacrificial layer on the isolation layer being covered by the capping pattern and the sacrificial layer projecting from the capping pattern being exposed;   oxidizing the exposed sacrificial layer; and   removing the capping pattern and the sacrificial layer remaining under the capping pattern.   
     
     
         16 . The method as claimed in  claim 15 , wherein the sacrificial layer is formed from a material having an etch selectivity with respect to the charge trap layer. 
     
     
         17 . The method as claimed in  claim 15 , wherein the sacrificial layer comprises silicon. 
     
     
         18 . The method as claimed in  claim 15 , wherein forming the capping pattern comprises:
 forming a capping layer filling a gap between the first and second fins; and   etching-back the capping layer.   
     
     
         19 . The method as claimed in  claim 15 , wherein the capping pattern is formed of a material layer having an etch selectivity with respect to the sacrificial layer. 
     
     
         20 . The method as claimed in  claim 15 , wherein the capping pattern comprises nitride.