FET Channel Having a Strained Lattice Structure Along Multiple Surfaces

Abstract

A channel 16 of a FinFET 10 has a channel core 24 and a channel envelope 32 , each made from a semiconductor material defining a different lattice structure to exploit strained silicon properties. A gate is coupled to the channel envelope through a gate dielectric. Exemplary materials are Si and Si X Ge 1−x , wherein 78<x<92. The channel core 24 has a top surface 26 of width w c and an upstanding surface 28, 30 of height h c , preferably oriented 90° to one another. The channel envelope 32 is in contact with the top 26 and upstanding surfaces 28, 30 so that the area of interface is increased as compared to contact only along the top surface 26, improving electrical conductivity and gate 18 control over the channel 16 . The height h c , can be tailored to enable a smaller scale FET 10 within a stabilized SRAM. Various methods of making the channel 16 are disclosed, including a mask and etch method, a handle wafer/carrier wafer method, and a shallow trench method. Embodiments and methods for FinFETs with one to four gates are disclosed.

1 - 20 . (canceled)  
     
     
         21 . A field effect transistor (FET) comprising: 
 a source, a drain, a channel, a gate electrode, and a gate dielectric, wherein the channel comprises a channel core defining a bottom surface and a top surface spaced from the bottom surface by laterally opposed sidewall surfaces disposed between the bottom surface and the top surface, wherein the channel core comprises a first semiconductor material defining a first lattice structure; the channel further comprising a channel envelope in contact with at least the top surface of the channel core, wherein the channel envelope comprises a second semiconductor material defining a second lattice structure that differs from the first lattice structure,    wherein one of the first and second lattice structures is one of stretched and compressed; and, wherein the gate electrode is coupled through the gate dielectric to the channel envelope only at a top surface of the channel envelope that is opposed to the top surface of the channel core.    
     
     
         22 . The FET of  claim 21 , wherein the first lattice structure is relaxed relative to the second lattice structure.  
     
     
         23 - 35 . (canceled)  
     
     
         36 . The field effect transistor of  claim 21 , wherein the first lattice structure is compressed relative to the second lattice structure.  
     
     
         37 . The field effect transistor of  claim 36 , wherein the second lattice structure is one of relaxed or stretched.  
     
     
         38 . The field effect transistor of  claim 21 , wherein one of the first and second semiconductor materials comprises silicon and germanium.  
     
     
         39 . The field effect transistor of  claim 21 , wherein the sidewall surfaces are parallel to a direction of current flow and are spaced from one another by a width that is less than or equal to a height of the sidewall surfaces.  
     
     
         40 . The field effect transistor of  claim 21 , wherein the sidewall surfaces are perpendicular to a substrate on which the field effect transistor is disposed.