US2008102568A1PendingUtilityA1

Soi bipolar transistors with reduced self heating

Assignee: IBMPriority: Jul 1, 2005Filed: Oct 28, 2007Published: May 1, 2008
Est. expiryJul 1, 2025(expired)· nominal 20-yr term from priority
H10D 84/401H10D 84/0109H10D 84/038H10D 86/201H10D 86/01
47
PatentIndex Score
0
Cited by
0
References
0
Claims

Abstract

A method for constructing a bipolar transistor comprising a collector, a base and an emitter, all located over a substrate, the method including steps of: creating a collector layer over the substrate; etching a path through the collector layer to the substrate; and filling the path with a heat-conductive material.

Claims

exact text as granted — not AI-modified
1 . A method for constructing a bipolar transistor comprising a collector, a base and an emitter, all located over a substrate, the method comprising steps of: 
 creating a collector layer over the substrate;    etching a path through the collector layer to the substrate; and    filling the path with a heat-conductive material.    
   
   
       2 . The method of  claim 1  wherein the heat-conductive material comprises a metal.  
   
   
       3 . The method of  claim 1  wherein the heat-conductive material comprises polysilicon.  
   
   
       4 . The method of  claim 1  further comprising removing any excess heat-conductive material.  
   
   
       5 . The method of  claim 1  wherein the step of depositing a collector layer comprises depositing an n-type material collector.  
   
   
       6 . The method of  claim 1  wherein the step of depositing a collector layer comprises depositing a p-type material collector.  
   
   
       7 . The method of  claim 1  further comprising creating an nMOS field effect transistor.  
   
   
       8 . The method of  claim 1  further comprising creating a pMOS field effect transistor.  
   
   
       9 . The method of  claim 1  further comprising: 
 locating the base over the collector; and    locating the emitter over the base, such that the bipolar transistor comprises a vertical structure.    
   
   
       10 . The method of claim further comprising: 
 locating the base and the emitter in a single layer above a buried oxide layer disposed above the substrate, such that the bipolar transistor comprises a lateral structure.

Join the waitlist — get patent alerts

Track US2008102568A1 — get alerts on status changes and closely related new filings.

We store only your email — no account needed. See our privacy policy.