Semiconductor package and methods of manufacturing the same

Abstract

A semiconductor package includes a semiconductor chip having first and second pads, a first insulation layer pattern formed on the semiconductor chip and having first and second openings that expose the first and the second pads, respectively, a first conductive layer pattern elongated along the first insulation layer pattern from the first pad, a first external terminal formed on the first conductive layer pattern, a second insulation layer pattern formed on the first conductive layer pattern and the first insulation layer pattern to expose the first external terminal and having a third opening in communication with the second opening, a second conductive layer pattern elongated along the second insulation layer pattern from the second pad, and a second external terminal formed on the second conductive layer pattern.

1 . A semiconductor package comprising:
 a semiconductor chip having a first pad and a second pad;   a first insulation layer pattern disposed on the semiconductor chip, the first insulation layer pattern defining a first opening exposing the first pad and a second opening exposing the second pad;   a first conductive layer pattern disposed on the first insulation layer pattern and electrically connected to the first pad;   a first external terminal disposed on the first conductive layer pattern;   a second insulation layer pattern disposed on the first conductive layer pattern and the first insulation layer pattern to expose the first external terminal, the second insulation layer pattern defining a third opening in communication with the second opening;   a second conductive layer pattern disposed on the second insulation layer pattern and electrically connected to the second pad; and   a second external terminal disposed on the second conductive layer pattern.   
   
   
       2 . The semiconductor package of  claim 1 , wherein the second external terminal is disposed higher above the semiconductor chip than the first external terminal. 
   
   
       3 . The semiconductor package of  claim 2 , wherein the second insulation layer pattern has a protrusion higher than a surface of the first external terminal, and the second external terminal is disposed on the protrusion. 
   
   
       4 . The semiconductor package of  claim 1 , wherein the first insulation layer pattern and the second insulation layer pattern comprise a ferrite material or a ferromagnetic material. 
   
   
       5 . The semiconductor package of  claim 1 , wherein the first and the second conductive layer patterns comprise aluminum. 
   
   
       6 . The semiconductor package of  claim 1 , wherein the first and the second external terminals comprise solder, gold or copper. 
   
   
       7 . A method of manufacturing a semiconductor package, comprising:
 forming a first insulation layer pattern defining first and second openings that expose first and second pads of a semiconductor chip, respectively, on the semiconductor chip having the first and second pads;   forming a first conductive layer pattern on the first insulation layer pattern and the first pad;   forming a first external terminal on the first conductive layer pattern;   forming a second insulation layer pattern defining a third opening in communication with the second opening on the first conductive layer pattern and the first insulation layer pattern, the second insulation layer pattern exposing a portion of the first external terminal;   forming a second conductive layer pattern on the second insulation layer pattern and the second pad; and   forming a second external terminal on the second conductive layer pattern.   
   
   
       8 . The method of  claim 7 , wherein forming the first insulation layer pattern comprises:
 forming a first insulation layer on the semiconductor substrate; and   etching the first insulation layer to form the first insulation layer pattern defining the first and the second openings.   
   
   
       9 . The method of  claim 8 , wherein the first insulation layer comprises a ferrite material or a ferromagnetic material. 
   
   
       10 . The method of  claim 7 , wherein forming the first conductive layer pattern comprises:
 forming a first conductive layer on the first insulation layer pattern and the first opening; and   etching the first conductive layer to form the first conductive layer pattern.   
   
   
       11 . The method of  claim 10 , wherein the first conductive layer comprises aluminum. 
   
   
       12 . The method of  claim 7 , wherein forming the second insulation layer pattern comprises:
 forming a second insulation layer on the first conductive layer pattern and the first insulation layer pattern so as to cover the first external terminal;   partially removing the second insulation layer to form a second insulation structure having a protrusion higher than the first external terminal; and   etching the second insulation structure to form the second insulation layer pattern defining the third opening.   
   
   
       13 . The method of  claim 12 , wherein the second insulation layer comprises a ferrite material or a ferromagnetic material. 
   
   
       14 . The method of  claim 7 , wherein forming the second conductive layer pattern comprises:
 forming a second conductive layer on the second insulation layer pattern, the second opening, and the third opening; and   etching the second conductive layer to form the second conductive layer pattern.   
   
   
       15 . The method of  claim 14 , wherein the second conductive layer comprises aluminum. 
   
   
       16 . The method of  claim 7 , wherein the first and the second external terminals comprise solder, gold or copper. 
   
   
       17 . A semiconductor package comprising:
 a semiconductor chip having a ground pad and a signal pad;   a first insulation layer pattern disposed on the semiconductor chip and defining a first opening and a second opening that expose the ground pad and the signal pad, respectively;   a first conductive layer pattern elongated along the first insulation layer pattern from the ground pad;   a ground terminal disposed on the first conductive layer pattern;   a second insulation layer pattern disposed on the first conductive layer pattern and the first insulation layer pattern to partially expose the ground terminal, and defining a third opening in communication with the second opening;   a second conductive layer pattern elongated along the second insulation layer pattern from the signal pad; and   a signal terminal disposed on the second conductive layer pattern.   
   
   
       18 . The semiconductor package of  claim 17 , wherein the signal terminal is located higher above the semiconductor chip than the ground terminal. 
   
   
       19 . The semiconductor package of  claim 17 , wherein the ground terminal has a width wider than that of the signal terminal.