Method for obtaining extreme selectivity of metal nitrides and metal oxides

Abstract

Methods for etching metal nitrides and metal oxides include using ultradilute HF solutions and buffered, low-pH HF solutions containing a minimal amount of the hydrofluoric acid species H 2 F 2 . The etchant can be used to selectively remove metal nitride layers relative to doped or undoped oxides, tungsten, polysilicon, and titanium nitride. A method is provided for producing an isolated capacitor, which can be used in a dynamic random access memory cell array, on a substrate using sacrificial layers selectively removed to expose outer surfaces of the bottom electrode.

1 . An integrated circuit including a capacitor comprising: 
 a conductive plug;    a tungsten container-shaped lower electrode;    a conformal capacitor dielectric extending over inner and outer surfaces of the lower electrode; and    an upper electrode extending over the conformal capacitor dielectric.    
   
   
       2 . The integrated circuit of  claim 1 , wherein the capacitor is part of a memory cell array.  
   
   
       3 . The integrated circuit of  claim 1 , wherein the capacitor is between about 50 nm and 160 nm from an adjacent capacitor in the memory cell array.  
   
   
       4 . The integrated circuit of  claim 3 , wherein the capacitor is between about 60 nm and 150 nm from an adjacent capacitor in the memory cell array.  
   
   
       5 . The integrated circuit of  claim 3 , wherein the conductive plug comprises an interconnect.  
   
   
       6 . The integrated circuit of  claim 3 , wherein the lower electrode is from about 100 Å to about 500 Å thick.  
   
   
       7 . The integrated circuit of  claim 3 , wherein the capacitor dielectric comprises at least one of AlN, Al 2 O 3 , HfN, HfO 2 , and Ta 2 O 5 .  
   
   
       8 . The integrated circuit of  claim 3 , wherein the capacitor dielectric is from about 10 nm to about 350 nm thick.  
   
   
       9 . The integrated circuit of  claim 3 , wherein the upper electrode comprises at least one of titanium nitride, tungsten, polysilicon, tungsten silicide, an elemental metal, an a metal alloy.  
   
   
       10 . An intermediate integrated circuit device structure comprising; 
 a structural layer over a substrate;    a plurality of conductive plugs beneath the structural layer;    a plurality of recesses in the structural layer over the conductive plugs; and    a metallic sacrificial layer within the recesses.    
   
   
       11 . The structure of  claim 10 , further comprising a cup-shaped lower electrode within the sacrificial layer.  
   
   
       12 . The structure of  claim 11 , wherein the lower electrode comprises a material selected from the group consisting of polysilicon, titanium nitride, and tungsten.  
   
   
       13 . The structure of  claim 11 , wherein the structural layer comprises a material selected from the group consisting of undoped silicon oxide, phosphosilicate glass and borophosphosilicate glass.  
   
   
       14 . The structure of  claim 11 , wherein the sacrificial layer comprises a material selected from the group consisting of metal oxides and metal nitrides.  
   
   
       15 . The structure of  claim 14 , wherein the sacrificial layer comprises a material selected from the group consisting of aluminum oxide, aluminum nitride, hafnium oxide, and hafnium nitride.  
   
   
       16 . The structure of  claim 15 , wherein the sacrificial layer comprises aluminum oxide.  
   
   
       17 . The structure of  claim 10 , wherein each recess is substantially centered over a conductive plug.  
   
   
       18 . The structure of  claim 10 , wherein each recess is from about 50 nm to about 160 nm from an adjacent recess.  
   
   
       19 . The integrated circuit of  claim 18 , wherein each recess is from about 60 nm to about 150 nm from an adjacent recess.