Method of forming guard ring parameterized cell structure in a hierarchical parameterized cell design, checking and verification system

Abstract

The invention displays a guard ring within an integrated circuit design by determining positions of the logic devices within the integrated circuit design, incorporating the guard ring into the integrated circuit design, and displaying the logic devices and the guard ring either graphically, semantically, or symbolically in a single display. The symbolic display comprises a parameterized symbol. The parameterized symbol displays parameters including the type of circuit, the type of guard ring and the efficiency of the guard ring. The invention displays the logic devices and the guard ring graphically by illustrating relative positions of the logic devices and the guard ring.

1 . A method of incorporating a guard ring into an integrated circuit design having logic devices, said method comprising: 
 identifying the type of circuit created by said logic devices;    selecting a type of guard ring based on said type of circuit;    incorporating said type of guard ring into said integrated circuit design; and    verifying the operation of said guard ring within said integrated circuit design.    
   
   
       2 . The method in  claim 1 , all the limitations of which are incorporated herein by reference, further comprising adding an electrostatic discharge (ESD) protection circuit to said integrated circuit design to protect said logic devices and identifying the type of ESD protection circuit added, wherein said process of selecting said type of guard ring is further based on said type of ESD protection circuit identified.  
   
   
       3 . The method in  claim 2 , all the limitations of which are incorporated herein by reference, wherein said type of ESD protection circuit comprises one of an input type, a power clamp type, and a type.  
   
   
       4 . The method in  claim 1 , all the limitations of which are incorporated herein by reference, wherein said type of circuit comprises one of a radio frequency (RF) circuit, a digital circuit, and an analog circuit.  
   
   
       5 . The method in  claim 1 , all the limitations of which are incorporated herein by reference, further comprising automatically adjusting the size and position of said guard ring as the size of said integrated circuit design is changed.  
   
   
       6 . The method in  claim 1 , all the limitations of which are incorporated herein by reference, further comprising adjusting said guard ring based on guard ring efficiency requirements.  
   
   
       7 . The method in  claim 1 , all the limitations of which are incorporated herein by reference, wherein said type of guard ring includes an enclosed guard ring with n-well rings, deep trench (DT), trench isolation (TI), p+ diffusion rings, and n+ diffusion rings.  
   
   
       8 . A method of incorporating at least one guard ring into a hierarchical integrated circuit design, said method comprising: 
 identifying the type of circuit located within a portion of said hierarchical integrated circuit design;    selecting a type of guard ring based on said type of circuit;    incorporating said type of guard ring into said portion of said hierarchical integrated circuit design;    verifying the operation of said guard ring within said portion of said hierarchical integrated circuit design; and    replacing said portion of said integrated circuit design with a cell having a guard ring within said hierarchical integrated circuit design.    
   
   
       9 . The method in  claim 8 , all the limitations of which are incorporated herein by reference, further comprising adding an electrostatic discharge (ESD) protection circuit to said integrated circuit design and identifying the type of ESD protection circuit added, wherein said process of selecting said type of guard ring is further based on said type of ESD protection circuit identified.  
   
   
       10 . The method in  claim 9 , all the limitations of which are incorporated herein by reference, wherein said type of ESD protection circuit comprises one of an input type, a power clamp type, and a rail to rail type.  
   
   
       11 . The method in  claim 8 , all the limitations of which are incorporated herein by reference, wherein said type of circuit comprises one of a radio frequency (RF) circuit, a digital circuit, and an analog circuit.  
   
   
       12 . The method in  claim 8 , all the limitations of which are incorporated herein by reference, further comprising automatically adjusting the size and position of said guard ring as the size of said integrated circuit design is changed.  
   
   
       13 . The method in  claim 8 , all the limitations of which are incorporated herein by reference, further comprising adjusting said guard ring based on guard ring efficiency requirements.  
   
   
       14 . The method in  claim 8 , all the limitations of which are incorporated herein by reference, wherein said type of guard ring includes an enclosed guard ring with n-well rings, deep trench (DT), trench isolation (TI), p+ diffusion rings, and n+ diffusion rings.  
   
   
       15 . A method of incorporating at least one guard ring into a hierarchical integrated circuit design, said method comprising: 
 identifying the type of circuit located within a portion of said hierarchical integrated circuit design;    selecting a type of guard ring based on said type of circuit;    incorporating said type of guard ring into said portion of said hierarchical integrated circuit design;    verifying the operation of said guard ring within said portion of said hierarchical integrated circuit design;    replacing said portion of said integrated circuit design with a cell having a guard ring within said hierarchical integrated circuit design; and    adding an electrostatic discharge (ESD) protection circuit to said integrated circuit design and identifying the type of ESD protection circuit added, wherein said process of selecting said type of guard ring is further based on said type of ESD protection circuit identified.    
   
   
       16 . The method in  claim 15 , all the limitations of which are incorporated herein by reference, wherein said type of ESD protection circuit comprises one of an input type, a power clamp type, and a rail to rail type.  
   
   
       17 . The method in  claim 15 , all the limitations of which are incorporated herein by reference, wherein said type of circuit comprises one of a radio frequency (RF) circuit, a digital circuit, and an analog circuit.  
   
   
       18 . The method in  claim 15 , all the limitations of which are incorporated herein by reference, further comprising automatically adjusting the size and position of said guard ring as the size of said integrated circuit design is changed.  
   
   
       19 . The method in  claim 15 , all the limitations of which are incorporated herein by reference, further comprising adjusting said guard ring based on guard ring efficiency requirements.  
   
   
       20 . The method in  claim 15 , all the limitations of which are incorporated herein by reference, wherein said type of guard ring includes an enclosed guard ring with n-well rings, deep trench (DT), trench isolation (TI), p+ diffusion rings, and n+ diffusion rings.