Ball grid array package and method thereof

Abstract

A ball grid array package includes a substrate, a chip, a plurality of pads, a solder mask, a plurality of partitioning walls, and a plurality of solder balls. The substrate has an upper surface and a lower surface opposite to the upper surface. The chip is disposed on the upper surface of the substrate. The pads are disposed on the lower surface of the substrate and electrically connected to the chip. The solder mask is disposed on the lower surface of the substrate. The partitioning walls are disposed on the solder mask and between the adjacent pads. The solder balls are respectively disposed on the pads.

1 . A method for manufacturing a BGA package comprising the following steps: 
 providing a substrate having an upper surface and a lower surface opposite to the upper surface;    providing a chip disposed on and electrically connected to the upper surface of the substrate;    applying a solder mask to the lower surface of the substrate and defining a plurality of pads; and    forming a plurality of partitioning walls on the solder mask wherein each partitioning wall is positioned between two adjacent pads.    
   
   
       2 . The method as claimed in  claim 1  further comprising a step of forming a plurality of flux units on the pads.  
   
   
       3 . The method as claimed in  claim 2  further comprising following steps: 
 providing a plurality of solder balls respectively positioned on the pads; and    reflowing the solder balls.    
   
   
       4 . The method as claimed in  claim 1 , wherein the chip is electrically connected to the substrate by a wire bonding technique.  
   
   
       5 . The method as claimed in  claim 1 , wherein the chip is electrically connected to the substrate by a flip chip technique.  
   
   
       6 . The method as claimed in  claim 4  further comprising a step of molding a package body for encapsulating the chip and a portion of the upper surface of the substrate.  
   
   
       7 . The method as claimed in  claim 1 , wherein the material of the partitioning walls is the same with that of the solder mask.  
   
   
       8 . The method as claimed in  claim 1 , wherein the partitioning walls are formed by a printed process.  
   
   
       9 . The method as claimed in  claim 1 , wherein the partitioning walls are formed by photolithography and etching processes.  
   
   
       10 . The method as claimed in  claim 5 , further comprising a step of molding a package body for encapsulating the chip and a portion of the upper surface of the substrate.