Correlation detection method, correlation detection apparatus, transmission diversity detection method and transmission diversity detection circuit

Abstract

A correlation detection apparatus detects a correlation between a reception signal and a spreading code. A logic circuit is operated with a chip clock. The logic circuit generates the spreading code of an offset unit of ½ chip according to a combination value of chips next to each other in a spreading code sequence, the spreading code sequence taking values of “+1” and “−1.” The logic circuit includes a ⅔ value converter that outputs a “0” when chips next to each other are not similar, outputs a “+1” when chips next to each other are of a value “+1”, and outputs a “−1” when chips next to each other are of a value “−1.”

1 . A correlation detection apparatus that detects a correlation between a reception signal and a spreading code, comprising: 
 a logic circuit operated with a chip clock, said logic circuit generating said spreading code of an offset unit of ½ chip according to a combination value of chips next to each other in a spreading code sequence, the spreading code sequence taking values of “+1” and “−1”, said logic circuit comprising a ⅔ value converter that outputs a “0” when chips next to each other are not similar, outputs a “+1” when chips next to each other are of a value “+1”, and outputs a “−1” when chips next to each other are of a value “−1”.    
   
   
       2 . A method for detecting a correlation between a reception signal and a spreading code generated with an offset unit of less than one chip in accordance with a combination value of chips next to each other in a spreading code sequence in which the spreading code sequence takes values of “+1” and “−1”, the method comprising: 
 outputting a “0” when chips next to each other are not similar;    outputting a “+1” when chips next to each other are of a value “+1”; and    outputting a “−1” when chips next to each other are of a value “−1”.    
   
   
       3 . The method of  claim 2 , further comprising: 
 using a logic circuit operated with a chip clock to generate the spreading code of an offset unit of ½ chip according in accordance with the combination value of chips next to each other in the spreading code sequence.    
   
   
       4 . The method of  claim 3 , wherein using a logic circuit comprises using a ⅔ value converter.