Dielectric layers and methods of forming the same

Abstract

High dielectric constant (high-k) materials are formed directly over oxidation-susceptible conductors such as silicon. A discontinuous layer is formed, with gaps between grains of the high-k material. Exposed conductor underneath the grain boundaries is oxidized or nitridized to form, e.g., silicon dioxide or silicon nitride, when exposed to oxygen or nitrogen source gases at elevated temperatures. This dielectric growth is preferential underneath the grain boundaries such that any oxidation or nitridation at the interface between the high-k material grains and covered conductor is not as extensive. The overall dielectric constant of the composite film is high, while leakage current paths between grains is reduced. Ultrathin high-k materials with low leakage current are thereby enabled.

1 . An integrated circuit, comprising: 
 a conductive structure; and    a discontinuous high-k dielectric layer directly overlying the conductive structure, the high-k dielectric layer comprising a plurality of crystalline grains and a plurality of gaps among the grains.    
   
   
       2 . The integrated circuit of  claim 1 , further comprising a second dielectric material over the conductive structure in the gaps of the high-k dielectric layer.  
   
   
       3 . The integrated circuit of  claim 2 , wherein the gaps among the grains filled by the second dielectric material cover less than about 20% of the conductive structure surface area.  
   
   
       4 . The integrated circuit of  claim 2 , wherein the gaps among the grains filled by the second dielectric material cover less than about 5% of the conductive structure surface area.  
   
   
       5 . The integrated circuit of  claim 2 , wherein the gaps among the grains filled by the second dielectric material cover less than about 1% of the conductive structure surface area.  
   
   
       6 . The method of  claim 2 , wherein the second dielectric material comprises a discontinuous layer.  
   
   
       7 . The integrated circuit of  claim 2 , wherein the second dielectric material comprises a layer of non-uniform thickness, having greater thickness in the gaps.  
   
   
       8 . The integrated circuit of  claim 2 , wherein the second dielectric material comprises an oxide of the conductive structure.  
   
   
       9 . The method of  claim 8 , wherein the conductive material comprises silicon and the second dielectric material comprises silicon dioxide.  
   
   
       10 . The method of  claim 2 , wherein the second dielectric material comprises a nitride of the conductive structure.  
   
   
       11 . The integrated circuit of  claim 10 , wherein the conductive structure comprises silicon and the second insulating material comprises silicon nitride.  
   
   
       12 . The integrated circuit of  claim 1 , further comprising an amorphous insulating material plugging conductive paths through the gaps.  
   
   
       13 . The integrated circuit of  claim 12 , wherein the amorphous insulating material comprises a continuous insulating layer filling the gaps and overlying the grains of the discontinuous high-k dielectric layer.  
   
   
       14 . The integrated circuit of  claim 1 , wherein the conductive structure comprises a channel region of a transistor and the high-k dielectric layer comprises a gate dielectric.  
   
   
       15 . The integrated circuit of  claim 1 , wherein the conductive structure comprises a storage electrode of an integrated capacitor in a memory cell.  
   
   
       16 . The integrated circuit of  claim 15 , wherein the conductive structure comprises hemispherical grained silicon.  
   
   
       17 . The integrated circuit of  claim 1 , wherein the conductive structure comprises a high surface area electrode.  
   
   
       18 . The integrated circuit of  claim 1 , wherein the gaps among the grains are defined by crystal shrinkage during crystallization of the high-k dielectric layer.  
   
   
       19 . The integrated circuit of  claim 1 , wherein the gaps among the grains are defined by islanding during deposition of the high-k dielectric layer.  
   
   
       20 . The integrated circuit of  claim 1 , wherein the conductive structure comprises a metal selected from the group consisting of tantalum, tungsten, aluminum and titanium.  
   
   
       21 . The integrated circuit of  claim 1 , wherein the high-k dielectric layer is selected from the group consisting of barium strontium titanate (BST), strontium titanate (ST), strontium bismuth tantalate (SBT) and lead strontium titanate (PST).  
   
   
       22 . The integrated circuit of  claim 1 , wherein the high-k dielectric layer is selected from the group consisting of zirconium oxide (ZrO 2 ) and hafnium oxide (HfO 2 ).  
   
   
       23 . The integrated circuit of  claim 1 , wherein the high-k dielectric layer is zirconium oxide.  
   
   
       24 . The integrated circuit of  claim 23 , wherein the high-k dielectric layer has a thickness between about 1 nm and 5 nm.