US2008093640A1PendingUtilityA1

Method for tuning epitaxial growth by interfacial doping and structure including same

Assignee: IBMPriority: Oct 26, 2005Filed: Dec 17, 2007Published: Apr 24, 2008
Est. expiryOct 26, 2025(expired)· nominal 20-yr term from priority
H10P 32/1412H10P 32/1204H10P 32/171H10P 30/204H10P 30/21H10D 30/608H10D 84/038H10D 84/017H10D 84/013H10D 30/0275H10D 62/151H10P 30/28
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Claims

Abstract

A method that allows for uniform, simultaneous epitaxial growth of a semiconductor material on dissimilarly doped semiconductor surfaces (n-type and p-type) that does not impart substrate thinning via a novel surface preparation scheme, as well as a structure that results from the implementation of this scheme into the process integration flow for integrated circuitry are provided. The method of the present invention can by used for the selective or nonselective epitaxial growth of semiconductor material from the dissimilar surfaces. More specifically, the invention comprises a method for counterdoping of n-FET and/or p-FET regions of silicon circuitry during the halo and/or extension implantation process utilizing a technique by which the surface characteristics of the two regions are made similar with respect to their response to wet or dry surface preparation and which renders the two previously dissimilar surfaces amenable to simultaneous epitaxial growth of raised source/drain structures; but not otherwise affecting the electrical performance of the resulting device.

Claims

exact text as granted — not AI-modified
1 . A semiconductor structure comprising: 
 at least one material region that is doped or undoped, wherein said at least one material region further includes an interfacial dopant region that changes the surface characteristic of said at least one material region in terms of its response to surface treatments and rate of epitaxial growth compared with another material region.    
   
   
       2 . The semiconductor structure of  claim 1  wherein said at least one material region is a doped surface of a field effect transistor.  
   
   
       3 . The semiconductor structure of  claim 2  wherein said doped surface is the source/drain region, the gate region or both.  
   
   
       4 . The semiconductor structure of  claim 1  wherein said interfacial doped region provides the at least one material region with similar surface characteristics as that of other material region.  
   
   
       5 . The semiconductor structure of claim I wherein said interfacial doped region provides the at least one material region with different surface characteristics as that of other material region.

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