High speed, low current consumption fifo circuit

Abstract

A FIFO circuit includes a write counter circuit, a memory circuit, a read counter circuit and a selector circuit. The write counter circuit counts a write clock signal during a valid period of input data, and outputs a write counter value. The memory circuit stores the input data in response to the write counter value. The read counter circuit counts a read clock signal when a decision is made that the memory circuit includes data that has not yet been read out, and outputs a read counter value. The read selector circuit reads data from the memory circuit in response to the read counter value. A small scale FIFO circuit can be obtained.

1 . A universal serial bus (USB) circuit having a first-in-first-out (FIFO) circuit including: 
 a write counter configured to count write clock pulses and to output a write counter value;    a read counter configured to count read clock pulses and to output a read counter value;    an address manager configured to output a data enable signal; and    a storage area configured to store data in accordance with the write clock pulses when the storage area receives the data, wherein    the write counter value indicates a write address in the storage area at which the data is to be written into,    the read counter value indicates a read address in the storage area from which the data is to be read out; and    the data enable signal indicates whether there is any data that has been written into the storage area but has not been read out from the storage area.    
   
   
       2 . The USB circuit according to  claim 1 , wherein 
 the address manager is further configured to manage a part of all empty addresses comprising a plurality of discrete or continuous bits of the write count value and the read count value.    
   
   
       3 . The USB circuit according to  claim 1 , wherein 
 the write counter is further configured to count the write clock pulses during a valid period of input data when the write counter receives the write clock pulses.    
   
   
       4 . The USB circuit according to  claim 1 , wherein 
 the storage area is further configured to output the data from the address indicated by the read counter value when the storage area receives the read clock pulses.