Methods for estimating power requirements of circuit designs

Abstract

One embodiment of the present invention is a method for estimating a power requirement of a circuit design that includes: (a) selecting a set of targeted Energy Arcs and/or Power Arcs; (b) creating one or more circuit states using the set of targeted Energy Arcs and/or Power Arcs; (c) back-tracing the one or more circuit states over one or more simulation clock cycles to form a start circuit state and a stimulus segment; and (d) recording the stimulus segment in a file.

1 . A method for estimating a power requirement of a circuit design that comprises: 
 selecting a set of targeted Energy Arcs and/or Power Arcs;    creating one or more circuit states using the set of targeted Energy and/or Power Arcs;    back-tracing the one or more circuit states over one or more simulation clock cycles to form a start circuit state and a stimulus segment; and    recording the stimulus segment in a file.    
   
   
       2 . The method of  claim 1  which further comprises: 
 obtaining stimulus segments from the file;    simulating the stimulus segments in forward time progression and determining which Event Arcs in Energy Arcs and/or which Condition Arcs in Power Arcs are satisfied at each stimulus clock cycle; and    recording data at each stimulus clock cycle that is utilized to estimate the power requirement in a second file.    
   
   
       3 . The method of  claim 1  which further comprises: 
 obtaining stimulus segments from the file;    simulating the stimulus segments in forward time progression and determining which Event Arcs in Energy Arcs and/or which Condition Arcs in Power Arcs are satisfied at each stimulus clock cycle; and    analyzing data at each stimulus clock cycle that is utilized to estimate the power requirement.    
   
   
       4 . The method of  claim 2  which further comprises: 
 analyzing the data in the second file to estimate the power requirement.    
   
   
       5 . The method of  claim 1  wherein the one or more simulation clock cycles is less than or equal to a maximum number.  
   
   
       6 . The method of  claim 1  wherein the set of targeted Energy Arcs and/or Power Arcs are chosen from a group of cells used in specifying the circuit design.  
   
   
       7 . The method of  claim 1  wherein the set of target Energy Arcs and/or Power Arcs are chosen from a group of cells that is logically equivalent or approximately logically equivalent to cells used in the circuit design.  
   
   
       8 . The method of  claim 6  wherein selecting comprises creating a W-neighborhood of cells and wherein the group is the W-neighborhood of cells.  
   
   
       9 . The method of  claim 7  wherein selecting comprises creating a W-neighborhood of Cells and wherein the group is the W-neighborhood of Cells.  
   
   
       10 . The method of  claim 8  wherein selecting includes utilizing a Macro Activity Model for Macro Cells.  
   
   
       11 . The method of  claim 9  wherein selecting includes utilizing a Macro Activity Model for Macro Cells.  
   
   
       12 . The method of  claim 1  wherein creating and back-tracing includes utilizing the Macro Activity Model for Macro cells.  
   
   
       13 . The method of  claim 1  wherein data in the file is simulated or analyzed or explored on the same circuit for a predetermined number of simulation clock cycles to determine an estimate of Peak Power.  
   
   
       14 . The method of  claim 8  wherein creating a W-neighborhood of Cells comprises selecting a single seed Cell or selecting multiple seed cells simultaneously.  
   
   
       15 . The method of  claim 9  wherein creating a W-neighborhood of Cells comprises selecting a single seed Cell or selecting multiple seed cells simultaneously.  
   
   
       16 . The method of  claim 1  further which further comprises using data in the file to simulate or analyze the circuit design using to explore switching activity.  
   
   
       17 . The method of  claim 1  which further comprises a user supplying information regarding functional behavior of the circuit design.  
   
   
       18 . The method of  claim 17  wherein the user supplied information is used in one or more of selecting a set of targeted Energy Arcs and/or Power Arcs, creating one or more circuit states, or back-tracing the one or more circuit states.  
   
   
       19 . The method of  claim 10  wherein the Macro Activity Model is specified in terms of sets of signal values on a boundary of the cell, and how often such signals are active.  
   
   
       20 . The method of  claim 1  wherein if cells used in the circuit design do not contain power information, energy information, or functional behavior information, or if the cells contain only a portion of such information, then such power information, energy information, or functional behavior information, or a missing portion of such information is provided by user input.  
   
   
       21 . The method of  claim 1  wherein a start state is assumed to exist under a simulation environment, and stimulus segments are created by forcing the start state on the circuit design in the simulation environment.  
   
   
       22 . The method of  claim 8  wherein W-neighborhoods are formed using different values of W-parameter in different areas of the circuit design.  
   
   
       23 . The method of  claim 8  which further comprises generating W-parameter values for W-neighborhoods by taking a random value for W between one and the total number of cells in the circuit for every new addition into the W-neighborhood.  
   
   
       24 . The method of  claim 1  wherein the circuit design includes a collection of statements describing logical operations of circuit signals, and Energy Arcs and/or Power Arcs are obtained by: 
 analyzing the circuit design to identify logical operations of signals; and finding their correspondence to a set of cells whose signal behaviors are provided and for which Energy Arc and/or Power Arc information is provided.    
   
   
       25 . The method of  claim 24  wherein the set of cells contain Energy and/or Power Arcs corresponding to signals and their logical operations.  
   
   
       26 . The method of  claim 24  wherein the logical operations include one or more of NAND, NOR, XOR, XNOR, AND, OR, MULTIPLEXOR, NOT, FLIP_FLOP, LATCH, or RAM.  
   
   
       27 . The method of  claim 24  wherein the set of cells is provided by a user.  
   
   
       28 . The method of  claim 24  wherein the circuit design is described at Register Transfer Level (RTL).  
   
   
       29 . The method of  claim 1  which further comprises creating Energy Arcs and/or Power Arcs for cells that do not contain Energy Arc and/or Power Arc information by: 
 modeling signal conditions in Energy Arcs or Power Arcs by taking various value combinations of signals at cell boundaries to form appropriate signal conditions.    
   
   
       30 . The method of  claim 29  wherein cells may be categorized into Combinational, Sequential, and Complex Cells.  
   
   
       31 . The method of  claim 1  wherein the circuit design includes a collection of statements describing logical operations of circuit signals, and Energy Arcs and/or Power Arcs are obtained by: 
 analyzing the circuit design to identify logical operations of signals;    considering such logical operations to take place inside a fictitious cell which approximately represents an equivalent technology cell;    using such equivalent technology cells, transforming the circuit design into a cell based representation; and    modeling signal conditions in Energy Arcs or Power Arcs by taking various value combinations of signals at cell boundaries to form appropriate signal conditions.