Self-aligned in-contact phase change memory device

Abstract

A memory cell and a method of making the same. An insulating material is deposited on a substrate. A via is produced in the substrate and a conductive lower block is disposed within the via. A step spacer comprised of insulating material is disposed in the via above the conductive lower block. Phase change material is disposed above the conductive lower block and bound within the step spacer. A conductive upper block comprised of conductive material is formed over the phase change material.

1 . A method of forming a memory cell, the method comprising:
 forming at least one insulating layer over a substrate;   forming a via in the insulating layer;   forming a conductive lower block in the via; forming a step spacer of insulating material in the via above the conductive lower block, the step spacer including a passage with a bottom aperture and a top aperture, the bottom aperture being smaller than the top aperture;   depositing phase change material in the via above the conductive lower block and within the step spacer; and   forming a conductive upper block over the phase change material.   
   
   
       2 . The method of  claim 1 , further comprising recessing the conductive lower block. 
   
   
       3 . The method of  claim 1 , further comprising depositing a heat-isolating conductive lower layer in the via at least between the conductive lower block and the phase change material. 
   
   
       4 . The method of  claim 1 , wherein forming the step spacer includes:
 depositing an insulating spacer layer within the via, the conformality of deposition of the insulating spacer layer being such that a cavity is formed by the insulating spacer layer; and   etching the insulating spacer layer such that the area below the cavity forms a ridge within the step spacer.   
   
   
       5 . The method of  claim 4 , further comprising forming a reentrant profile of the via prior to the deposition of the insulating spacer layer. 
   
   
       6 . The method of  claim 5 , wherein forming the reentrant via profile includes:
 forming a first insulating layer over the conductive lower block;   forming a second insulating layer over the first insulating layer; and   etching the first and second insulating layers such that the second insulating layer overhangs the first insulating layer.   
   
   
       7 . The method of  claim 4 , further comprising depositing insulating material above the conductive lower block and in the via, the insulating material being thicker than the radius of the via. 
   
   
       8 . The method of  claim 7 , wherein the formation of the step spacer is performed such that the cavity of the step spacer along a center axial cross section of the step spacer is substantially T-shaped. 
   
   
       9 . The method of  claim 1 , further comprising:
 recessing the phase change material into the via; and   depositing a heat-isolating conductive upper layer between at least the phase change material and the conductive upper block.   
   
   
       10 . A memory cell comprising:
 a substrate;   an insulating material formed over the substrate with a via formed therein;   a conductive lower block at the bottom of the via;   a step spacer made of insulating material disposed over the conductive lower block, the step spacer including a passage;   phase change material disposed above the conductive lower block and within the step spacer; and   a conductive upper block disposed above the phase change material.   
   
   
       11 . The memory cell of  claim 10 , further comprising a heat-isolating conductive lower layer disposed between the conductive lower block and the phase change material. 
   
   
       12 . The memory cell of  claim 10 , wherein the step spacer includes a bottom aperture and a top aperture, the bottom aperture being smaller than the top aperture. 
   
   
       13 . The memory cell of  claim 12 , wherein the step spacer includes a ridge between the bottom aperture and the top aperture along a radial axis and within the passage. 
   
   
       14 . The memory cell of  claim 10 , wherein the cavity of the step spacer is substantially T-shaped along a center axial cross section of the step spacer. 
   
   
       15 . The memory cell of  claim 10 , further comprising a heat-isolating conductive upper layer disposed between the phase change material and the conductive upper block. 
   
   
       16 . The memory cell of  claim 10 , wherein the conductive upper block is outside of the via. 
   
   
       17 . An integrated circuit comprising one or more memory cells, at least one of the memory cells comprising:
 a substrate;   an insulating material formed over the substrate with a via formed therein;   a conductive lower block at the bottom of the via;   a step spacer made of insulating material disposed over the conductive lower block, the step spacer including a passage;   phase change material disposed above the conductive lower block and within the step spacer; and   a conductive upper block disposed above the phase change material.   
   
   
       18 . The integrated circuit of  claim 17 , further comprising:
 a heat-isolating conductive lower layer disposed between the conductive lower block and the phase change material; and   a heat-isolating conductive upper layer disposed between the conductive upper block and the phase change material.   
   
   
       19 . The integrated circuit of  claim 17 , wherein the step spacer includes a bottom aperture and a top aperture, the bottom aperture being smaller than the top aperture. 
   
   
       20 . The integrated circuit of  claim 19 , wherein the step spacer includes a ridge between the bottom aperture and the top aperture along a radial axis and within the passage. 
   
   
       21 . The integrated circuit of  claim 17 , wherein the cavity of the step spacer along a center axial cross section of the step spacer is substantially T-shaped.