US2008090317A1PendingUtilityA1

Nanotip diode electroluminescence device

Assignee: SHARP LAB OF AMERICA INCPriority: Mar 23, 2005Filed: Nov 29, 2007Published: Apr 17, 2008
Est. expiryMar 23, 2025(expired)· nominal 20-yr term from priority
H10H 20/8512H10H 20/821H10H 20/818H10H 20/826H10H 20/813B82Y 20/00Y10S977/834
52
PatentIndex Score
0
Cited by
0
References
0
Claims

Abstract

A nanotip electroluminescence (EL) diode and a method are provided for fabricating said device. The method comprises: forming a plurality of Si nanotip diodes; forming a phosphor layer overlying the nanotip diode; and, forming a top electrode overlying the phosphor layer. The nanotip diodes are formed by: forming a Si substrate with a top surface; forming a Si p-well; forming an n+ layer of Si, having a thickness in the range of 30 to 300 nanometers (nm) overlying the Si p-well; forming a reactive ion etching (RIE)-induced polymer grass overlying the substrate top surface; using the RIE-induced polymer grass as a mask, etching areas of the substrate not covered by the mask; and, forming the nanotip diodes in areas of the substrate covered by the mask.

Claims

exact text as granted — not AI-modified
1 . A method for fabricating a silicon (Si) nanotip electroluminescence (EL) diode, the method comprising: 
 forming a plurality of Si nanotip diodes, where each nanotip diode is p/n junction nanotip structure;    forming a phosphor layer overlying the nanotip diodes; and    forming a top electrode overlying the phosphor layer.    
     
     
         2 . The method of  claim 1  wherein forming the nanotip diodes includes: 
 forming a reactive ion etching (RIE)-induced polymer grass overlying a top surface of the substrate;    using the RIE-induced polymer grass as a mask, etching areas of the substrate not covered by the mask; and    forming the nanotip diodes in areas of the substrate covered by the mask.    
     
     
         3 . The method of  claim 2  wherein forming the nanotip diodes includes: 
 prior to forming the RIE-induced polymer grass, forming a Si p-well; and,    forming an n+ layer of Si, having a thickness in the range of 30 to 300 nanometers (nm), overlying the Si p-well as follows: 
 doping the Si substrate with a density in the range of 1×10 16  to 1×10 18  per cubic centimeter (/cm 3 ); and  
 implanting an ion selected from the group including phosphorus and arsenic at an energy in the range of 20 keV to 100 keV.  
   
     
     
         4 . The method of  claim 3  wherein forming the RIE-induced polymer grass includes: 
 introducing a mixture of oxygen and carbon tetrafluoride;    exciting the mixture using a radio frequency (RF); and    etching the Si substrate for a time in the range of 10 seconds to 5 minutes.    
     
     
         5 . The method of  claim 2  wherein etching areas of the substrate using the RIE-induced polymer grass as a mask includes: 
 etching using SF 6  and C 4 F 8  chemistries;    etching exposed portions of the n+ layer; and    exposing regions of the underlying p-well.    
     
     
         6 . The method of  claim 5  wherein exposing regions of the underlying p-well includes etching into the p-well a depth greater than about 2 nanometers (nm).  
     
     
         7 . The method of  claim 5  wherein forming the phosphor layer includes forming a Si oxide phosphor layer.  
     
     
         8 . The method of  claim 7  wherein forming the Si oxide phosphor layer includes: 
 following the exposure of underlying regions of the p-well, removing the remaining RIE-induced polymer grass, exposing n+ Si regions;    thermally oxidizing the exposed n+ and exposed p-well Si regions;    growing 1 to 5 nanometers (nm) of silicon oxide; and    depositing silicon oxide overlying the thermally grown silicon oxide.    
     
     
         9 . (canceled)  
     
     
         10 . The method of  claim 1  wherein forming the phosphor layer includes forming a rare earth element-doped insulator where the rare earth is selected from the group including erbium (Er), ytterbium (Yb), cerium (Ce), praseodymium (Pr), and terbium (Tb), and the insulator is a material selected from the group including Si oxide and Si nitride.  
     
     
         11 . The method of  claim 10  wherein forming the phosphor layer includes: 
 depositing an insulator with a rare earth doping density in the range of 1 at % (atomic weight %) to 5 at %; and    thermal annealing at a temperature in the range of 600° C. to 1200° C. for a time in the range of 10 to 200 minutes.    
     
     
         12 . The method of  claim 1  wherein forming nanotip diodes includes forming nanotip diodes with ends; and 
 the method further comprising:    following the forming of the phosphor layer, chemical-mechanical polishing (CMPing) the phosphor layer, exposing the nanotip diode ends.    
     
     
         13 . The method of  claim 1  wherein forming the top electrode includes forming a top electrode from a material selected from the group including indium tin oxide (ITO), Zinc oxyfluoride, and conductive plastics.  
     
     
         14 . The method of  claim 1  wherein forming nanotip diodes includes forming nanotip diodes having a base size of about 50 nanometers, or less.  
     
     
         15 . The method of  claim 1  wherein forming the nanotip diodes includes forming nanotip diodes having a height in the range of 50 to 500 nm.  
     
     
         16 . The method of  claim 1  wherein forming the nanotip diodes includes forming nanotip diodes having a density of greater than 100 per square micrometer.  
     
     
         17 . The method of  claim 1  wherein forming the plurality of Si nanotip diodes includes forming a plurality of isolated regions, each region including a plurality of nanotip diodes; 
 wherein forming the phosphor layer overlying the nanotip diodes includes forming a phosphor layer region overlying each region of nanotip diodes; and    wherein forming a top electrode overlying the phosphor layer includes forming an isolated top electrode overlying each phosphor layer region.    
     
     
         18 - 30 . (canceled)  
     
     
         31 . A method for fabricating a silicon (Si) nanotip electroluminescence (EL) diode, the method comprising: 
 forming a plurality of isolated regions, each region including a plurality of nanotip diodes;    forming a phosphor layer region overlying each region of nanotip diodes; and    forming an isolated top electrode overlying each phosphor layer region.

Join the waitlist — get patent alerts

Track US2008090317A1 — get alerts on status changes and closely related new filings.

We store only your email — no account needed. See our privacy policy.