Method for making hydrogen using a gold containing water-gas shift catalyst

Abstract

The present invention relates to a method for oxidizing CO, comprising: passing a first feed comprising CO and a second feed comprising oxygen, in an oxidation zone, over a catalyst comprising highly dispersed gold on sulfated zirconia, at oxidation conditions, to produce an effluent comprising a lower level of CO than in the first feed.

1 . An apparatus for use in performing a floating point multiply-accumulate operation, comprising: 
 a plurality of latches that contain a plurality of operands for the operation;    a carry-save adder, coupled to the latches, that receives the operands and performs a carry-save add operation on the operands to produce a first result; and    a logic block, coupled to the carry-save adder, that receives the first result and performs a carry-lookahead add operation on the first result to produce a second result, the logic block having a logic circuit that performs a logic operation on the second result based upon a control signal to produce a value for use in the floating point multiply-accumulate operation, the logic circuit including a redundant stage that processes a most significant bit.    
     
     
         2 . The apparatus of  claim 1  wherein the logic circuit performs the logic operation on a most significant bit of the second result.  
     
     
         3 . The apparatus of  claim 2  wherein the logic circuit performs an exclusive-OR operation between the most significant bit and the control signal.  
     
     
         4 . (canceled)  
     
     
         5 . The apparatus of  claim 1  wherein the redundant logic stage performs the logic operation on the most significant bit in parallel with at least a portion of the carry-lookahead add operation.  
     
     
         6 . The apparatus of  claim 1  wherein the logic circuit performs the logic operation to produce a shift value for use in the floating point multiply-accumulate operation.  
     
     
         7 . The apparatus of  claim 1 , further including a control circuit for generating the control signal.  
     
     
         8 . The apparatus of  claim 7  wherein the control circuit generates the control signal based upon a single instruction, multiple data (SIMD) operation.  
     
     
         9 . The apparatus of  claim 7  wherein the control signal is a pair of complementary signals and wherein the control circuit generates the pair of complementary signals.  
     
     
         10 . The apparatus of  claim 1  wherein the logic block includes a carry-lookahead adder having complementary logic circuits for providing complementary outputs as the second result.  
     
     
         11 . A method implemented on a floating point multiply-accumulate device for use in performing a floating point multiply-accumulate operation, comprising: 
 receiving a plurality of operands for the operation;    performing a carry-save add operation on the operands to produce a first result; performing a carry-lookahead add operation on the first result to produce a second result;    receiving a control signal; and    performing a logic operation on the second result based upon the control signal to produce a value for use in the floating point multiply-accumulate operation;    performing the logic operation on a most significant bit of the second result, and    performing an exclusive-OR operation between the most significant bit and control.    
     
     
         12 - 13 . (canceled)  
     
     
         14 . The method of  claim 11  wherein the performing the logic operation step includes using a redundant logic stage for processing the most significant bit in a carry-lookahead adder circuit.  
     
     
         15 . The method of  claim 14  wherein the using the redundant logic stage includes processing the most significant bit in parallel with at least a portion of the step of performing the carry-lookahead add operation.  
     
     
         16 . The method of  claim 11  wherein the performing the logic operation step includes producing a shift value for use in the floating point multiply-accumulate operation.  
     
     
         17 . The method of  claim 11 , further including generating the control signal.  
     
     
         18 . The method of  claim 17  wherein the generating step 
 includes generating the control signal based upon a Single Instruction Multiple Data (SIMD) operation.    
     
     
         19 . The method of  claim 17  wherein the generating step includes generating a pair of complementary signals as the control signal.  
     
     
         20 . The method of  claim 11  wherein the performing the carry-lookahead add operation step includes using complementary logic circuits for the carry-lookahead add operation to provide complementary outputs as the second result.