Method for testing flash memory power loss recovery

Abstract

Non-volatile memory device, driver, and method is described that utilizes write or erase cycle tracking to interrupt or stop a non-volatile memory programming or erase operation at a selected point to interrupt/stop execution or simulate power loss at a specific point. This ability allows for a deterministic and repeatable testing process of all write or erase cycles of a non-volatile command where the state of floating gate memory cells are changed in the non-volatile memory device. Additionally, this ability to utilize write or erase cycle tracking to interrupt or stop a non-volatile memory programming operation or erasing operation at any selected point enables simulation of power loss at each point in a selected operation that a non-volatile floating gate memory cell is programmed or erased, allowing for improved, deterministic testing of the power loss recovery cycle and faster code/design change verification.

1 . A method of operating a non-volatile memory comprising: 
 counting a number of internal non-volatile memory cell write and/or erase actions in a non-volatile memory occurring during execution of a selected memory operation; and    halting execution of the selected memory operation in the non-volatile memory at a selected count of the internal non-volatile memory cell write and/or erase actions.    
   
   
       2 . The method of  claim 1 , further comprising: 
 resetting the non-volatile memory or executing power loss recovery routines on the non-volatile memory after halting execution of the selected memory operation at the selected count of the internal non-volatile memory cell write and/or erase actions.    
   
   
       3 . The method of  claim 1 , wherein halting execution of the selected memory operation in the non-volatile memory at a selected count of the internal non-volatile memory cell write and/or erase actions further comprises at the selected count of the internal non-volatile memory cell write and/or erase actions, counting clock cycles or execution steps of a command execution logic state machine and halting execution of a current internal non-volatile memory cell write and/or erase action of the memory operation at a selected number of clock cycles or execution steps of the command execution logic state machine.  
   
   
       4 . The method of  claim 1 , further comprising loading an internal register in the non-volatile memory with the selected number of internal non-volatile memory cell write and/or erase actions.  
   
   
       5 . The method of  claim 1 , further comprising: 
 changing the selected count of internal non-volatile memory cell write and/or erase actions;    re-executing the non-volatile memory operation;    counting a number of internal non-volatile memory cell write and/or erase actions; and    interrupting execution of the non-volatile memory operation at the changed selected count of internal non-volatile memory cell write and/or erase actions.    
   
   
       6 . The method of  claim 5 , further comprising changing the non-volatile memory operation to a second non-volatile memory operation after all possible counts of internal non-volatile memory cell write and/or erase actions of the non-volatile memory operation have been tested.  
   
   
       7 . The method of  claim 1 , further comprising examining a state of one or more registers and/or array contents of the non-volatile memory after halting execution.  
   
   
       8 . A method of operating a non-volatile memory system comprising: 
 counting a number of internal non-volatile memory write and/or erase operations in a non-volatile memory system having a non-volatile memory controller coupled to one or more non-volatile memory devices, wherein the number of internal non-volatile memory write and/or erase operations occur during execution of an externally provided non-volatile memory command to the non-volatile memory controller; and    halting execution of the externally provided memory command at a selected count of the internal non-volatile memory write and/or erase operations.    
   
   
       9 . The method of  claim 8 , further comprising: 
 executing a power loss recovery routine on the non-volatile memory system after halting execution of the externally provided non-volatile memory command at the selected count of the internal non-volatile memory write and/or erase operations.    
   
   
       10 . The method of  claim 8 , wherein halting execution of the externally provided non-volatile memory command in the non-volatile memory system at a selected count of the internal non-volatile memory write and/or erase operations further comprises at the selected count of the internal non-volatile memory write and/or erase operations, counting a selected number of clock cycles before halting execution of a current internal non-volatile memory write and/or erase operation of the externally provided non-volatile memory command or counting a selected number of execution steps of the non-volatile memory controller before halting execution of a current internal non-volatile memory write and/or erase operation of the externally provided non-volatile memory command at the selected number of execution steps of the non-volatile memory controller.  
   
   
       11 . The method of  claim 8 , further comprising externally loading an internal register in the non-volatile memory controller of the non-volatile memory system with the selected number of internal non-volatile memory write and/or erase operations to halt at.  
   
   
       12 . The method of  claim 8 , further comprising: 
 changing the selected count of internal non-volatile memory write and/or erase operations;    re-executing the externally provided non-volatile memory command;    counting a number of internal non-volatile memory write and/or erase operations; and    halting execution of the externally provided non-volatile memory command at the changed selected count of internal non-volatile memory write and/or erase operations.    
   
   
       13 . The method of  claim 8 , further comprising examining one or more registers and/or data contents of the non-volatile memory controller and the one or more non-volatile memory devices of the non-volatile memory system after halting execution of the externally provided non-volatile memory command.  
   
   
       14 . A system comprising: 
 one or more non-volatile memory devices coupled to a host;    wherein the system is adapted to count a selected number of non-volatile memory write and/or erase operations to one or more registers and one or more array locations of a selected non-volatile memory device of the one or more non-volatile memory devices during execution of a memory command and halt execution of the memory command at a selected count of the non-volatile memory write and/or erase operations.    
   
   
       15 . The system of  claim 14 , wherein the system is adapted to execute a power loss recovery routine on the one or more non-volatile memory devices after halting execution of the memory command at the selected count of the non-volatile memory write and/or erase operations.  
   
   
       16 . The system of  claim 14 , wherein the system is adapted to halt execution of the memory command in the system at the selected count of the non-volatile memory write and/or erase operations by either counting a selected number of clock cycles before halting execution of a current non-volatile memory write and/or erase operation at the selected count of non-volatile write and/or erase operations, or by counting a selected number of execution steps of the host before halting execution of a current non-volatile memory write and/or erase operation at the selected count of non-volatile write and/or erase operations at the selected number of execution steps.  
   
   
       17 . The system of  claim 14 , wherein the system is adapted to load an internal register in the selected non-volatile memory device of the system with one of a selected number of internal non-volatile memory write and/or erase operations to halt at, a selected number of clock cycles to halt at, or a selected number of execution steps of a command execution logic state machine to halt at.  
   
   
       18 . The system of  claim 14 , wherein the system is further adapted to change the selected count of non-volatile memory write and/or erase operations and re-execute the memory command, count a number of non-volatile memory write and/or erase operations, and halt execution of the memory command at the changed selected count of non-volatile memory write and/or erase operations.  
   
   
       19 . The system of  claim 14 , wherein the system is adapted to examine one or more registers and/or data contents of the host and the one or more non-volatile memory devices of the system after halting execution of the memory command.  
   
   
       20 . A memory comprising: 
 a memory array;    one or more non-volatile control registers;    a control circuit; and    a count register;    wherein the memory is adapted to count a number of internal writes and/or erases to the memory array and/or the one or more control registers during execution of a memory command and stop execution of the memory command when the count of internal writes and/or erases matches a count number stored in the count register.    
   
   
       21 . The memory of  claim 20 , wherein the memory is adapted to stop execution of the memory command when the count of internal writes and/or erases matches the count number stored in the count register by stopping execution of a selected internal write and/or erase either after a selected number of execution steps of a command execution logic state machine, or after a selected number of clock cycles.  
   
   
       22 . The memory of  claim 20 , wherein the memory is adapted to execute a power loss recovery routine after stopping execution of the memory command.  
   
   
       23 . A method of operating a non-volatile memory device driver comprising: 
 receiving an external non-volatile memory command;    counting a number of internal non-volatile memory write and/or erase actions in a non-volatile memory occurring during execution of the external memory non-volatile command; and    halting execution of the non-volatile memory command at a selected count of the internal non-volatile memory write and/or erase actions.    
   
   
       24 . The method of  claim 23 , wherein halting execution of the non-volatile memory command at a selected count of the internal non-volatile memory write and/or erase actions further comprises halting execution of the non-volatile memory command at the selected count of internal non-volatile memory write and/or erase actions by halting execution of a selected internal non-volatile memory write and/or erase action after one of a selected time period has passed, a selected number of execution steps of a command execution logic state machine have occurred, and a selected number of clock cycles have occurred.  
   
   
       25 . The method of  claim 23 , further comprising executing a power loss recovery routine after halting execution of the external non-volatile memory command at the selected count of the internal non-volatile memory write and/or erase actions.