Semiconductor device having reduced-damage active region and method of manufacturing the same

Abstract

A semiconductor device according to example embodiments may include a substrate having an NMOS area and a PMOS area, isolation regions and well regions formed in the substrate, gate patterns formed on the substrate between the isolation regions, source/drain regions formed in the substrate between the gate patterns and the isolation regions, source/drain silicide regions formed in the source/drain regions, a tensile stress layer formed on the NMOS area, and a compressive stress layer formed on the PMOS area, wherein the tensile stress layer and compressive stress layer may overlap at a boundary region of the NMOS area and the PMOS area. The semiconductor devices according to example embodiments and methods of manufacturing the same may increase the stress effect on the active region while reducing or preventing surface damage to the active region.

1 . A semiconductor device comprising:
 a substrate having an NMOS area and a PMOS area;   isolation regions and well regions in the substrate;   gate patterns on the substrate between the isolation regions;   source/drain regions in the substrate between the gate patterns and the isolation regions;   source/drain silicide regions in the source/drain regions;   a tensile stress layer on the NMOS area; and   a compressive stress layer on the PMOS area, wherein the tensile stress layer and compressive stress layer overlap at a boundary region of the NMOS area and the PMOS area.   
   
   
       2 . The semiconductor device of  claim 1 , wherein a top surface of one or more of the source/drain regions is at the same level as an interfacial surface between the gate patterns and the substrate. 
   
   
       3 . The semiconductor device of  claim 1 , wherein a top surface of one or more of the source/drain silicide regions is higher than an interfacial surface between the gate patterns and the substrate. 
   
   
       4 . The semiconductor device of  claim 1 , wherein the source/drain regions comprise:
 low-concentration source/drain regions that partially overlap with corresponding gate patterns, the low-concentration source/drain regions at a first depth from a surface of the substrate; and   high-concentration source/drain regions that do not overlap with the corresponding gate patterns, the high-concentration source/drain regions at a second depth from the surface of the substrate, the second depth being deeper than the first depth.   
   
   
       5 . The semiconductor device of  claim 4 , wherein the source/drain silicide regions are on the high-concentration source/drain regions, and a horizontal distance from the gate patterns to the high-concentration source/drain regions is smaller than a horizontal distance from the gate patterns to the source/drain silicide regions. 
   
   
       6 . The semiconductor device of  claim 4 , wherein the source/drain silicide regions are on the high-concentration source/drain regions, and a horizontal distance from the gate patterns to the high-concentration source/drain regions is the same as a horizontal distance from the gate patterns to the source/drain silicide regions. 
   
   
       7 . The semiconductor device of  claim 1 , wherein the gate patterns comprise:
 a gate insulating layer on the substrate;   a gate electrode on the gate insulating layer;   a gate spacer on sidewalls of the gate insulating layer and the gate electrode; and   a gate silicide region on the gate electrode, a top surface of the gate silicide region being higher than a top portion of the gate spacer.   
   
   
       8 . The semiconductor device of  claim 1 , further comprising a tensile buffer layer under the tensile stress layer. 
   
   
       9 . The semiconductor device of  claim 8 , further comprising a compressive buffer layer under the compressive stress layer. 
   
   
       10 . The semiconductor device of  claim 9 , wherein the compressive buffer layer is thicker than the tensile buffer layer. 
   
   
       11 . A method of manufacturing a semiconductor device, comprising:
 forming isolation regions and well regions in a substrate having an NMOS area and a PMOS area;   forming gate patterns on the substrate so that the gate patterns are disposed between the isolation regions;   forming first source/drain regions between the gate patterns and the isolation regions, the first source/drain regions having first ion-concentrations;   forming first spacers on sidewalls of the gate patterns;   forming second spacers on sidewalls of the first spacers;   forming source/drain silicide regions in the source/drain regions;   removing the second spacers;   removing the first spacers;   forming a tensile stress layer on the NMOS area; and   forming a compressive stress layer on the PMOS area.   
   
   
       12 . The method of  claim 11 , wherein the first spacers are formed of SiGe. 
   
   
       13 . The method of  claim 11 , wherein the second spacers surround the first spacers. 
   
   
       14 . The method of  claim 11 , wherein the second spacers are formed of silicon nitride. 
   
   
       15 . The method of  claim 11 , further comprising:
 forming second source/drain regions after forming the first spacers, the second source/drain regions having second ion concentrations that are higher than the first ion concentrations of the first source/drain regions.   
   
   
       16 . The method of  claim 15 , wherein the silicide regions are formed on the second source/drain regions. 
   
   
       17 . The method of  claim 11 , further comprising:
 forming a tensile buffer layer on the NMOS area and the PMOS area prior to forming the tensile stress layer.   
   
   
       18 . The method of  claim 17 , wherein the tensile buffer layer is used as an etch-stop layer when the tensile stress layer is patterned. 
   
   
       19 . The method of  claim 11 , further comprising:
 forming a compressive buffer layer on the NMOS area and the PMOS area prior to forming the compressive stress layer.   
   
   
       20 . The method of  claim 19 , wherein the compressive buffer layer is used as an etch-stop layer when the compressive stress layer is patterned.