Semiconductor integrated circuit device and method for designing the same

Abstract

A semiconductor integrated circuit device has a plurality of design patterns composed of circuit elements or wires formed on a substrate. The respective finished sizes of the plurality of design patterns have a plurality of minimum size values which differ from one design pattern to another depending on the geometric feature of each of the design patterns.

1 - 22 . (canceled)  
   
   
       23 . A semiconductor integrated circuit device comprising: 
 a plurality of design patterns composed of circuit elements or wires formed on a substrate, the plurality of design patterns having a plurality of minimum size values which differ from one design pattern to another depending on different required specifications dependent on usage modes thereof.    
   
   
       24 . The semiconductor integrated circuit device of  claim 23 , wherein 
 the circuit elements are composed of a plurality of memory elements and    the usage modes and the required specifications are set to tolerate a fault in some of the plurality of memory elements.    
   
   
       25 . The semiconductor integrated circuit device of  claim 23 , wherein 
 the circuit elements are memory elements and    the usage modes and the required specifications are such that the memory elements do not retain data during standby.    
   
   
       26 - 47 . (canceled)  
   
   
       48 . A method for designing a semiconductor integrated circuit device, the method comprising the step of: 
 forming, on a substrate, a plurality of design patterns composed of circuit elements or wires, wherein    a plurality of design rules having different values are applied to the plurality of design patterns depending on different required specifications dependent on respective usage modes of the design patterns.    
   
   
       49 . The method of  claim 48 , wherein 
 the circuit elements are composed of a plurality of memory elements and    the usage modes and the required specifications are set to tolerate a fault in some of the plurality of memory elements.    
   
   
       50 . The method of  claim 48 , wherein 
 the circuit elements are memory elements and    the usage modes and the required specifications are set such that the memory elements do not retain data during standby.