Fets with self-aligned bodies and backgate holes

Abstract

Embodiments of the invention disclose a design structure for a FET with a shallow source/drain region, a deep channel region, a gate stack and a back gate that is surrounded by dielectric. The FET structure also includes halo or pocket implants that extend through the entire depth of the channel region. Because a portion of the halo and well doping of the channel is deeper than the source/drain depth, better threshold voltage and process control is achieved. A back-gated FET structure is also provided having a first dielectric layer in this structure that runs under the shallow source/drain region between the channel region and the back gate. This first dielectric layer extends from under the source/drain regions on either side of the back gate and is in contact with a second dielectric such that the back gate is bounded on each side or isolated by dielectric.

1 . A design structure embodied in a machine readable medium used in a design process, the design structure comprising a silicon on insulator (SOI) field effect transistor (FET) comprising: 
 a substrate having a top surface;    a gate over said top surface of said substrate;    a channel region in said substrate below said gate; and    source and drain regions in said substrate on opposite sides of said channel,    wherein said channel region extends a further distance from said top surface into said substrate when compared to said source and drain regions.    
   
   
       2 . The design structure according to  claim 1 , all the limitations of which are incorporated herein by reference, wherein a part of said channel region is partially depleted.  
   
   
       3 . The design structure according to  claim 1 , all the limitations of which are incorporated herein by reference, wherein said channel region is fully depleted.  
   
   
       4 . The design structure according to  claim 1 , all the limitations of which are incorporated herein by reference, wherein said channel region comprises a halo implant on opposite sides of said channel and wherein said halo implant extends a further distance from said top surface into said substrate when compared to said source and drain regions.  
   
   
       5 . The design structure according to  claim 1 , all the limitations of which are incorporated herein by reference, wherein said FET comprises a back gate positioned below said channel region and positioned a further distance from said top surface into said substrate than said channel region.  
   
   
       6 . The design structure according to  claim 5 , all the limitations of which are incorporated herein by reference, wherein said back gate is positioned into said substrate so that said substrate surrounds said back gate on at least two sides of said back gate.  
   
   
       7 . The design structure according to  claim 1 , all the limitations of which are incorporated herein by reference, wherein said design structure comprises a netlist which describes a circuit.  
   
   
       8 . The design structure according to  claim 1 , all the limitations of which are incorporated herein by reference, wherein said design structure resides on a storage medium as a data format used for the exchange of layout data of integrated circuits.  
   
   
       9 . The design structure according to  claim 1 , all the limitations of which are incorporated herein by reference, wherein said design structure includes at least one of test data files, characterization data, verification data, and design specifications.  
   
   
       10 . A design structure embodied in a machine readable medium used in a design process, the design structure comprising a silicon on insulator (SOI) field effect transistor (FET) comprising: 
 a substrate having a top surface;    a gate over said top surface of said substrate;    a channel region in said substrate below said gate;    source and drain regions in said substrate on opposite sides of said channel, and    a halo implant on opposite sides of said channel,    wherein said channel region extends a further distance from said top surface into said substrate when compared to said source and drain regions and wherein said halo implant extends a further distance from said top surface into said substrate when compared to said source and drain regions.    
   
   
       11 . The design structure according to  claim 10 , all the limitations of which are incorporated herein by reference, wherein a part of said channel region is partially depleted.  
   
   
       12 . The design structure according to  claim 10 , all the limitations of which are incorporated herein by reference, wherein said channel region is fully depleted.  
   
   
       13 . The design structure according to  claim 10 , all the limitations of which are incorporated herein by reference, wherein said FET comprises a back gate positioned below said channel region and positioned a further distance from said top surface into said substrate than said channel region.  
   
   
       14 . The design structure according to  claim 10 , all the limitations of which are incorporated herein by reference, wherein said back gate is positioned into said substrate so that said substrate surrounds said back gate on at least two sides of said back gate.  
   
   
       15 . The design structure according to  claim 10 , all the limitations of which are incorporated herein by reference, wherein said design structure comprises a netlist which describes a circuit.  
   
   
       16 . The design structure according to  claim 10 , all the limitations of which are incorporated herein by reference, all the limitations of which are incorporated herein by reference, wherein said design structure resides on a storage medium as a data format used for the exchange of layout data of integrated circuits.  
   
   
       17 . The design structure according to  claim 10 , all the limitations of which are incorporated herein by reference, wherein said design structure includes at least one of test data files, characterization data, verification data, and design specifications.