Data processor for modifying and executing operation of instruction code

Abstract

A MOD_SAT instruction indicating that a 16 bit saturation is to be carried out with respect to the operation of one of instructions executed in parallel is placed in the left container and an ADD instruction is placed in the right container. When the instruction decode unit decodes these instructions, the instruction decode unit indicates that the instruction execution unit executes the ADD instruction accompanying a saturation process. Accordingly, the operation of a great number of instructions can be modified by combining instructions and, therefore, the basic instruction length can be made short and it becomes possible to increase the code efficiency.

1 . A data processor comprising: an instruction fetch unit fetching an instruction code; an instruction decode unit decoding the instruction code fetched by said instruction fetch unit; an instruction execution unit executing the instruction in response to a result of decoding by said instruction decode unit; and a circuit, in the case that the instruction code indicates a modification of operations of a plurality of other instruction codes, modifying said operations and allowing said instruction execution unit to execute the modified operations of said plurality of other instruction codes.  
   
   
       2 . The data processor according to  claim 1 , wherein said instruction execution unit executes a process including a saturation process in a case that the instruction execution unit executes the modified operation of said plurality of other instruction codes  
   
   
       3 . The data processor according to  claim 1 , wherein said instruction execution unit executes the operation designated by said plurality of other instruction codes for a plurality of pieces of data in the case that the instruction execution unit executes the modified operations of said plurality of other instruction codes.  
   
   
       4 . The data processor according to  claim 3 , wherein said instruction execution unit divides data, which is an object of processing, into a plurality of pieces of data and executes the operation designated by said plurality of other instruction codes for each of the plurality of divided pieces of data in the case that the instruction execution unit executes the modified operations of said plurality of other instruction codes.  
   
   
       5 . The data processor according to  claim 3 , wherein said instruction execution unit executes the operation designated by said plurality of other instruction codes for a plurality of data including data designated by said plurality of other instruction codes and data implicitly designated by said plurality of other instruction codes based on predetermined rules in the case that said instruction execution unit executes the modified operations of said plurality of other instruction codes.  
   
   
       6 . A data processor comprising: an instruction fetch unit fetching an instruction code; an instruction decode unit decoding the instruction code fetched by said instruction fetch unit; an instruction execution unit executing the instruction in response to a result of decoding by said instruction decode unit; and a circuit, in the case that the instruction code indicates a modification of an operation of an instruction code of the next instruction, modifying said operation and allowing said instruction execution unit to execute the modified operation of the instruction code of said next instruction.  
   
   
       7 . The data processor according to  claim 6 , wherein said instruction execution unit executes a process including a saturation process in a case that the instruction execution unit executes the modified operation of the instruction code of said next instruction.  
   
   
       8 . The data processor according to  claim 6 , wherein said instruction execution unit executes the operation designated by said instruction code of said next instruction for a plurality of pieces of data in the case that the instruction execution unit executes the modified operation of the instruction code of said next instruction.  
   
   
       9 . The data processor according to  claim 8 , wherein said instruction execution unit divides data, which is an object of processing, into a plurality of pieces of data and executes the operation designated by said instruction code of said next instruction for each of the plurality of divided pieces of data in the case that the instruction execution unit executes the modified operation of the instruction code of said next instruction.  
   
   
       10 . The data processor according to  claim 8 , wherein said instruction execution unit executes the operation designated by said instruction code of said next instruction for a plurality of data including data designated by said instruction code of said next instruction and data implicitly designated by said instruction code of said next instruction based on predetermined rules in the case that said instruction execution unit executes said instruction code of said next instruction.  
   
   
       11 . A data processor comprising: an instruction fetch unit fetching an instruction code; an instruction decode unit decoding the instruction code fetched by said instruction fetch unit; an instruction execution unit executing the instruction in response to a result of decoding by said instruction decode unit; and a circuit, in the case that the instruction code indicates a modification of an operation of other instruction code, modifying said operation and allowing said instruction execution unit to execute a modified operation of said other instruction code, wherein said instruction execution unit executes a process including a saturation process in a case that the instruction execution unit executes the modified operation of said other instruction code.  
   
   
       12 . The data processor according to  claim 11 , wherein said other instruction code is an operation instruction.  
   
   
       13 . The data processor according to  claim 11 , wherein said other instruction code is a store instruction.  
   
   
       14 . The data processor according to  claim 11 , wherein said other instruction code is a transfer instruction.  
   
   
       15 .- 20 . (canceled)