Integrated circuit chips with fine-line metal and over-passivation metal

Abstract

An integrated circuit chip includes a silicon substrate, a first circuit in or over said silicon substrate, a second circuit device in or over said silicon substrate, a dielectric structure over said silicon substrate, a first interconnecting structure in said dielectric structure, a first pad connected to said first node of said voltage regulator through said first interconnecting structure, a second interconnecting structure in said dielectric structure, a second pad connected to said first node of said internal circuit through said second interconnecting structure, a passivation layer over said dielectric structure, wherein multiple opening in said passivation layer exposes said first and second pads, and a third interconnecting structure over said passivation layer and over said first and second pads.

What is claimed is: 
     
         1 . A method for fabricating an integrated circuit chip comprising:
 providing a silicon substrate, an ESD circuit in or over said silicon substrate, an internal circuit in or over said silicon substrate, wherein said internal circuit comprises an NMOS transistor, wherein a ratio of a physical channel width of said NMOS transistor to a channel length of said NMOS transistor ranges from 0.1 to 20, a dielectric structure over said silicon substrate, a first interconnecting structure over said silicon substrate and in or over said dielectric structure, wherein said first interconnecting structure is connected to a first node of said ESD circuit, a first pad over said silicon substrate, wherein said first pad is connected to first node of said ESD circuit through said first interconnecting structure, a second interconnecting structure over said silicon substrate and in or over said dielectric structure, wherein said second interconnecting structure is connected to a first node of said internal circuit, a second pad over said silicon substrate, wherein said second pad is connected to said first node of said internal circuit through said second interconnecting structure, and a passivation layer over said dielectric structure, wherein a first opening in said passivation layer exposes said first pad, and a second opening in said passivation layer exposes said second pad; and   forming a third interconnecting structure over said passivation layer and over said first and second pads, wherein said first node of said ESD circuit is connected to said first node of said internal circuit through, in sequence, said first interconnecting structure, said first pad, said third interconnecting structure, said second pad and said second interconnecting structure, and wherein said third interconnecting structure comprises a patterned circuit layer formed by a process comprising forming a first metal layer over said passivation layer, forming a first photoresist layer over said first metal layer, an opening in said first photoresist layer exposing said first metal layer, forming a second metal layer over said first metal layer exposed by said opening in said first photoresist layer, removing said first photoresist layer, forming a second photoresist layer over said second metal layer, an opening in said second photoresist layer exposing said second metal layer, forming a third metal layer over said second metal layer exposed by said opening in said second photoresist layer, removing said second photoresist layer, and removing said first metal layer not under said second metal layer.   
     
     
         2 . The method of  claim 1  further comprising forming a polymer layer over said passivation layer, followed by said forming said patterned circuit layer. 
     
     
         3 . The method of  claim 1  further comprising forming a polymer layer over said patterned circuit layer. 
     
     
         4 . The method of  claim 3 , after said forming said polymer layer, further comprising polishing said polymer layer. 
     
     
         5 . The method of  claim 1 , wherein said forming said second metal layer comprises electroplating a copper layer having a thickness between 2 and 30 micrometers over said first metal layer exposed by said opening in said first photoresist layer. 
     
     
         6 . The method of  claim 1 , wherein forming said third metal layer comprises electroplating a copper layer having a thickness between 2 and 30 micrometers over said second metal layer exposed by said opening in said second photoresist layer. 
     
     
         7 . The method of  claim 1 , wherein said forming said first metal layer comprises a sputtering process. 
     
     
         8 . A method for fabricating an integrated circuit chip comprising:
 providing a silicon substrate, an I/O circuit in or over said silicon substrate, wherein said I/O circuit comprises a first NMOS transistor, wherein a ratio of a physic channel width of said first NMOS transistor to a physical channel length of said first NMOS transistor ranges from 20 to 20,000, an internal circuit in or over said silicon substrate, wherein said internal circuit comprises an NMOS transistor, wherein a ratio of a physical channel width of said NMOS transistor to a channel length of said NMOS transistor ranges from 0.1 to 20, a dielectric structure over said silicon substrate, a first interconnecting structure over said silicon substrate and in or over said dielectric structure, wherein said first interconnecting structure is connected to a first node of said I/O circuit, a first pad over said silicon substrate, wherein said first pad is connected to first node of said I/O circuit through said first interconnecting structure, a second interconnecting structure over said silicon substrate and in or over said dielectric structure, wherein said second interconnecting structure is connected to a first node of said internal circuit, a second pad over said silicon substrate, wherein said second pad is connected to said first node of said internal circuit through said second interconnecting structure, and a passivation layer over said dielectric structure, wherein a first opening in said passivation layer exposes said first pad, and a second opening in said passivation layer exposes said second pad; and   forming a third interconnecting structure over said passivation layer and over said first and second pads, wherein said first node of said I/O circuit is connected to said first node of said internal circuit through, in sequence, said first interconnecting structure, said first pad, said third interconnecting structure, said second pad and said second interconnecting structure, and wherein said third interconnecting structure comprises a patterned circuit layer formed by a process comprising forming a first metal layer over said passivation layer, forming a first photoresist layer over said first metal layer, an opening in said first photoresist layer exposing said first metal layer, forming a second metal layer over said first metal layer exposed by said opening in said first photoresist layer, removing said first photoresist layer, forming a second photoresist layer over said second metal layer, an opening in said second photoresist layer exposing said second metal layer, forming a third metal layer over said second metal layer exposed by said opening in said second photoresist layer, removing said second photoresist layer, and removing said first metal layer not under said second metal layer.   
     
     
         9 . The method of  claim 8  further comprising forming a polymer layer over said passivation layer, followed by said forming said patterned circuit layer. 
     
     
         10 . The method of  claim 8  further comprising forming a polymer layer over said patterned circuit layer. 
     
     
         11 . The method of  claim 10 , after said forming said polymer layer, further comprising polishing said polymer layer. 
     
     
         12 . The method of  claim 8 , wherein said forming said second metal layer comprises electroplating a copper layer having a thickness between 2 and 30 micrometers over said first metal layer exposed by said opening in said first photoresist layer. 
     
     
         13 . The method of  claim 8 , wherein forming said third metal layer comprises electroplating a copper layer having a thickness between 2 and 30 micrometers over said second metal layer exposed by said opening in said second photoresist layer. 
     
     
         14 . The method of  claim 8 , wherein said forming said first metal layer comprises a sputtering process. 
     
     
         15 . A method for fabricating an integrated circuit chip comprising:
 providing a silicon substrate, a first internal circuit in or over said silicon substrate, wherein said first internal circuit comprises a first NMOS transistor, wherein a ratio of a physical channel width of said first NMOS transistor to a channel length of said first NMOS transistor ranges from 0.1 to 20, a second internal circuit in or over said silicon substrate, wherein said second internal circuit comprises a second NMOS transistor, wherein a ratio of a physical channel width of said second NMOS transistor to a channel length of said second NMOS transistor ranges from 0.1 to 20, a dielectric structure over said silicon substrate, a first interconnecting structure over said silicon substrate and in or over said dielectric structure, wherein said first interconnecting structure is connected to a first node of said first internal circuit, a first pad over said silicon substrate, wherein said first pad is connected to first node of said first internal circuit through said first interconnecting structure, a second interconnecting structure over said silicon substrate and in or over said dielectric structure, wherein said second interconnecting structure is connected to a first node of said second internal circuit, a second pad over said silicon substrate, wherein said second pad is connected to said first node of said second internal circuit through said second interconnecting structure, and a passivation layer over said dielectric structure, wherein a first opening in said passivation layer exposes said first pad, and a second opening in said passivation layer exposes said second pad; and   forming a third interconnecting structure over said passivation layer and over said first and second pads, wherein said first node of said first internal circuit is connected to said first node of said second internal circuit through, in sequence, said first interconnecting structure, said first pad, said third interconnecting structure, said second pad and said second interconnecting structure, and wherein said third interconnecting structure comprises a patterned circuit layer formed by a process comprising forming a first metal layer over said passivation layer, forming a first photoresist layer over said first metal layer, an opening in said first photoresist layer exposing said first metal layer, forming a second metal layer over said first metal layer exposed by said opening in said first photoresist layer, removing said first photoresist layer, forming a second photoresist layer over said second metal layer, an opening in said second photoresist layer exposing said second metal layer, forming a third metal layer over said second metal layer exposed by said opening in said second photoresist layer, removing said second photoresist layer, and removing said first metal layer not under said second metal layer   
     
     
         16 . The method of  claim 15  further comprising forming a polymer layer over said passivation layer, followed by said forming said patterned circuit layer. 
     
     
         17 . The method of  claim 15  further comprising forming a polymer layer over said patterned circuit layer. 
     
     
         18 . The method of  claim 17 , after said forming said polymer layer, further comprising polishing said polymer layer. 
     
     
         19 . The method of  claim 15 , wherein said forming said second metal layer comprises electroplating a copper layer having a thickness between 2 and 30 micrometers over said first metal layer exposed by said opening in said first photoresist layer. 
     
     
         20 . The method of  claim 15 , wherein forming said third metal layer comprises electroplating a copper layer having a thickness between 2 and 30 micrometers over said second metal layer exposed by said opening in said second photoresist layer.