Chip-on-board package having flip chip assembly structure and manufacturing method thereof

Abstract

A chip-on-board (COB) package has a flip chip assembly structure and is used for an integrated circuit (IC) card. The COB package has conductive patterns as contact terminals on an outer surface of a non-conductive film, and an IC chip on an inner surface of the film. The film has a number of holes through which the conductive patterns are partly exposed. A number of conductive bumps on an active surface of the IC chip face the inner surface of the film and enter corresponding holes in the non-conductive film to mechanically join and electrically couple to the conductive patterns. The disclosed COB package and a related manufacturing method allow a reduction in production cost, simplified process, better electrical connections, and improved reliability.

1 . A method of manufacturing a chip-on-board package, the method comprising: 
 forming a plurality of holes through a non-conductive film having a first surface and a second surface opposite the first surface;    forming conductive patterns on the first surface of the non-conductive film and exposed through the holes;    forming conductive bumps on an active surface of an integrated circuit chip; and    disposing the integrated circuit chip relative to the second surface of the non-conductive film to make insertable the conductive bumps into the holes of the non-conductive film.    
   
   
       2 . A method of  claim 1 , further comprising mechanically joining and electrically coupling the conductive bumps and the conductive patterns by way of the holes.  
   
   
       3 . The method of  claim 2 , wherein the forming of the holes is carried out using a punch.  
   
   
       4 . The method of  claim 2 , wherein the forming of the conductive patterns includes bonding a metal plate to the first surface of the non-conductive film and photo-etching the metal plate.  
   
   
       5 . The method of  claim 2 , wherein the forming of the conductive bumps is carried out using at least one of electroplating and stud bumping.  
   
   
       6 . The method of  claim 2 , further comprising: 
 interposing a non-conductive adhesive between the active surface of the integrated circuit chip and the second surface of the non-conductive film.