Methods of Manufacturing Non-Volatile Memory Devices

Abstract

In a method of manufacturing a non-volatile memory device, a conductive structure is formed on a substrate. The conductive structure includes a tunnel oxide pattern, a first conductive pattern, a pad oxide pattern and a hard mask pattern. A trench is formed on the substrate using the conductive structure as an etching mask. An inner oxide layer is formed on an inner wall of the trench and sidewalls of the tunnel oxide pattern and the first conductive pattern. The inner oxide layer is cured, thereby forming a silicon nitride layer on the inner oxide layer. A device isolation pattern is formed in the trench, and the hard mask pattern and the pad oxide pattern are removed from the substrate. A dielectric layer and a second conductive pattern are formed on the substrate. Accordingly, the silicon nitride layer prevents-hydrogen (H) atoms from leaking into the device isolation pattern.

1 . A method of forming a non-volatile memory device, comprising the steps of:
 forming a tunnel oxide layer pattern and a floating gate electrode pattern on a semiconductor substrate;   forming a trench in a portion of the semiconductor substrate extending adjacent the floating gate electrode pattern;   forming an electrically insulating layer on a sidewall of the trench;   curing the electrically insulating layer for a sufficient duration to increase a degree of impermeability of hydrogen atoms therein;   filling the trench with an electrical isolation region that extends on the cured electrically insulating layer; and   forming a control gate electrode pattern on the floating gate electrode pattern.   
   
   
       2 . The method of  claim 1 , wherein curing the electrically insulating layer comprises nitrating the electrically insulating layer to form a silicon nitride layer on the electrically insulating layer. 
   
   
       3 . The method of  claim 2 , wherein nitrating the electrically insulating layer comprises nitrating the electrically insulating layer by performing a plasma nitration process on the electrically insulating layer at a temperature in a range from about 15° C. to about 100° C. 
   
   
       4 . The method of  claim 1 , wherein curing the electrically insulating layer comprises annealing the electrically insulating layer using a gas comprising nitrogen, deuterium, fluorine and/or chlorine. 
   
   
       5 . The method of  claim 1 , wherein forming an electrically insulating layer comprises forming an electrically insulating layer on a sidewall of the floating gate electrode. 
   
   
       6 . The method of  claim 5 , wherein forming an electrically insulating layer comprises forming an electrically insulating layer directly on an upper surface of the floating gate electrode. 
   
   
       7 . A method of forming a non-volatile memory device, comprising the steps of:
 forming a trench in a portion of a semiconductor substrate;   forming an electrically insulating layer on a sidewall of the trench;   curing the electrically insulating layer for a sufficient duration to increase a degree of impermeability of hydrogen atoms therein;   filling the trench with an electrical isolation region that extends on the cured electrically insulating layer and protrudes vertically relative to a surface of the semiconductor substrate; then   forming a tunnel oxide layer on the surface of the semiconductor substrate, at a location adjacent the cured electrically insulating layer; and   forming a floating gate electrode pattern that extends on the tunnel oxide layer and on a sidewall of a vertically protruding portion of the electrical isolation region.   
   
   
       8 . The method of  claim 7 , wherein said step of forming a tunnel oxide layer comprises thermally oxidizing the surface of the semiconductor substrate using the cured electrically insulating layer as an oxidation mask. 
   
   
       9 . The method of  claim 7 , wherein curing the electrically insulating layer comprises nitrating the electrically insulating layer to form a silicon nitride layer on the electrically insulating layer. 
   
   
       10 . The method of  claim 9 , wherein nitrating the electrically insulating layer comprises nitrating the electrically insulating layer by performing a plasma nitration process on the electrically insulating layer at a temperature in a range from about 15° C. to about 100° C. 
   
   
       11 . The method of  claim 7 , wherein curing the electrically insulating layer comprises annealing the electrically insulating layer using a gas comprising nitrogen, deuterium, fluorine and/or chlorine. 
   
   
       12 . A method of forming a non-volatile memory device, comprising the steps of:
 forming a tunnel oxide layer pattern and a floating gate electrode pattern on a semiconductor substrate;   forming a trench in a portion of the semiconductor substrate extending adjacent the floating gate electrode pattern;   forming a first electrically insulating layer on a sidewall of the trench; then   filling the trench with a first electrical isolation region that extends on the first electrically insulating layer,   etching back the first electrical isolation region and the first electrically insulating layer for a sufficient duration to expose a portion of the sidewall of the trench;   forming a second electrically insulating layer on the exposed portion of the sidewall of the trench;   curing the second electrically insulating layer for a sufficient duration to increase a degree of impermeability of hydrogen atoms therein; and   refilling the trench with a second electrical isolation region.   
   
   
       13 . The method of  claim 12 , wherein refilling the trench is followed by etching back the second electrical isolation region and the cured second electrically insulating layer to expose a sidewall of the floating gate electrode pattern. 
   
   
       14 . The method of  claim 13 , wherein etching back the second electrical isolation region and the cured second electrically insulating layer is followed by forming an inter-gate dielectric layer on the exposed sidewall of the floating gate electrode pattern and forming a control electrode pattern on the inter-gate dielectric layer. 
   
   
       15 . The method of  claim 12 , wherein curing the second electrically insulating layer comprises nitrating the second electrically insulating layer to form a silicon nitride layer on the second electrically insulating layer. 
   
   
       16 . The method of  claim 15 , wherein nitrating the second electrically insulating layer comprises nitrating the second electrically insulating layer by performing a plasma nitration process on the second electrically insulating layer at a temperature in a range from about 15° C. to about 100° C. 
   
   
       17 . The method of  claim 12 , wherein curing the second electrically insulating layer comprises annealing the second electrically insulating layer using a gas comprising nitrogen, deuterium, fluorine and/or chlorine. 
   
   
       18 . A method of manufacturing a non-volatile memory device, comprising:
 forming a conductive structure on a substrate, the conductive structure including a tunnel oxide pattern, a first conductive pattern, a pad oxide pattern and a hard mask pattern that are sequentially stacked on the substrate;   forming a trench on the substrate by an etching process using the conductive structure as an etching mask;   forming an inner oxide layer on an inner wall of the trench and sidewalls of the tunnel oxide pattern and the first conductive pattern;   curing the inner oxide layer, so that hydrogen (H) atoms are prevented from leaking from a surface of the substrate;   forming a device isolation pattern in the trench by filling up the trench with an insulation material;   removing the hard mask pattern and the pad oxide pattern from the substrate to expose the first conductive pattern; and   forming a dielectric layer and a second conductive pattern on the first conductive pattern.   
   
   
       19 . The method of  claim 18 , wherein curing the inner oxide layer includes nitrating the inner oxide layer to form a silicon nitride layer on the inner oxide layer. 
   
   
       20 . The method of  claim 19 , wherein nitrating the inner oxide layer is performed by a plasma nitration process at a temperature of about 15° C. to about 100° C. 
   
   
       21 . The method of  claim 18 , wherein curing the inner oxide layer includes annealing the inner oxide layer using a gas having atoms of which an atomic weight is greater than that of hydrogen (H), the atoms including any one selected from the group consisting of nitrogen (N), deuterium (D), fluorine (F) and chlorine (Cl). 
   
   
       22 . The method of  claim 18 , after removing the hard mask pattern and the pad oxide pattern, further comprising removing a portion of the device isolation pattern to partially expose sidewalls of the first conductive pattern. 
   
   
       23 . A method of manufacturing a non-volatile memory device, comprising:
 forming a conductive structure on a substrate, the conductive structure including a tunnel oxide pattern, a first conductive pattern, a pad oxide pattern and a hard mask pattern that are sequentially stacked on the substrate;   forming a trench on the substrate by an etching process using the conductive structure as an etching mask;   forming a first device isolation pattern in the trench by partially filling up the trench with an insulation material;   forming a buffer oxide pattern on a surface of the first device isolation pattern, on an inner wall of the trench and on sidewalls of the tunnel oxide pattern and the first conductive pattern;   curing the buffer oxide pattern, so that hydrogen (H) atoms are prevented from leaking from a surface of the substrate;   forming a second device isolation pattern in the trench by filling up the trench with an insulation material;   removing the hard mask pattern and the pad oxide pattern from the substrate to expose the first conductive pattern; and   forming a dielectric layer and a second conductive pattern on the first conductive pattern.   
   
   
       24 . The method of  claim 23 , wherein curing the buffer oxide pattern includes nitrating the buffer oxide pattern to form a silicon nitride pattern on the buffer oxide pattern. 
   
   
       25 . The method of  claim 24 , wherein nitrating the buffer oxide pattern is performed by a plasma nitration process at a temperature of about 15° C. to about 100° C. 
   
   
       26 . The method of  claim 23 , wherein curing the buffer oxide pattern includes annealing the buffer oxide pattern using a gas having atoms of which an atomic weight is greater than that of hydrogen (H), the atoms including any one selected from the group consisting of nitrogen (N), deuterium (D), fluorine (F) and chlorine (Cl). 
   
   
       27 . The method of  claim 23 , wherein forming a first device isolation pattern includes:
 forming a preliminary device isolation layer in the trench by filling up the trench with an insulation material;   forming a preliminary device isolation pattern by planarizing the preliminary device isolation layer until a surface of the hard mask pattern is exposed; and   removing a portion of the preliminary device isolation pattern by a wet etching process.   
   
   
       28 . The method of  claim 23 , wherein a top surface of the first device isolation pattern is lower than a top surface of the substrate. 
   
   
       29 . The method of  claim 23 , after removing the hard mask pattern and the pad oxide pattern, further comprising removing a portion of the second device isolation pattern to partially expose sidewalls of the first conductive pattern. 
   
   
       30 . A method of manufacturing a non-volatile memory device, comprising:
 forming a conductive structure on a substrate, the conductive structure including a pad oxide pattern and a hard mask pattern that are sequentially stacked on the substrate;   forming a trench on the substrate by an etching process using the conductive structure as an etching mask;   forming an inner oxide layer on an inner wall of the trench and sidewalls of the pad oxide pattern;   curing the inner oxide pattern, so that hydrogen (H) atoms are prevented from leaking from a surface of the substrate;   removing the hard mask pattern and the pad oxide pattern from the substrate to form an opening through which a surface of the substrate is exposed;   forming a tunnel oxide pattern and a first conductive pattern in the opening; and   forming a dielectric layer and a second conductive pattern on the first conductive pattern.   
   
   
       31 . The method of  claim 30 , curing the inner oxide layer includes nitrating the inner oxide layer to form a silicon nitride layer on the inner oxide layer. 
   
   
       32 . The method of  claim 31 , wherein nitrating the inner oxide layer is performed by a plasma nitration process at a temperature of about 15° C. to about 100° C. 
   
   
       33 . The method of  claim 30 , wherein curing the inner oxide layer includes annealing the inner oxide layer using a gas having atoms of which an atomic weight is greater than that of hydrogen (H), the atoms including any one selected from the group consisting of nitrogen (N), deuterium (D), fluorine (F) and chlorine (Cl). 
   
   
       34 . The method of  claim 30 , after removing the hard mask pattern and the pad oxide pattern, further comprising removing a portion of the device isolation pattern to partially expose sidewalls of the first conductive pattern. 
   
   
       35 . A method of manufacturing a non-volatile memory device, comprising:
 forming a conductive structure on a substrate, the conductive structure including a pad oxide pattern and a hard mask pattern that are sequentially stacked on the substrate;   forming a trench on the substrate by an etching process using the conductive structure as an etching mask;   forming a first device isolation pattern in the trench by partially filling up the trench with an insulation material;   forming a buffer oxide pattern on a surface of the first device isolation pattern, an inner wall of the trench, sidewalls of the pad oxide pattern, and sidewalls and a top surface of the hard mask pattern;   curing the buffer oxide pattern to prevent hydrogen (H) atoms from leaking from a surface of the substrate;   forming a second device isolation pattern in the trench by filling up the trench with an insulation material;   removing the hard mask pattern and the pad oxide pattern from the substrate to form an opening through which a surface of the substrate is exposed;   forming a tunnel oxide pattern and a first conductive pattern in the opening; and   forming a dielectric layer and a second conductive pattern on the first conductive pattern.   
   
   
       36 . The method of  claim 35 , wherein curing the buffer oxide pattern includes nitrating the buffer oxide pattern to form a silicon nitride pattern on the buffer oxide pattern. 
   
   
       37 . The method of  claim 36 , wherein nitrating the buffer oxide pattern is performed by a plasma nitration process at a temperature of about 15° C. to about 100° C. 
   
   
       38 . The method of  claim 35 , wherein curing the buffer oxide pattern includes annealing the buffer oxide pattern using a gas having atoms of which an atomic weight is greater than that of hydrogen (H), the atoms including any one selected from the group consisting of nitrogen (N), deuterium (D), fluorine (F) and chlorine (Cl). 
   
   
       39 . The method of  claim 35 , wherein a top surface of the first device isolation pattern is lower than a surface of the substrate. 
   
   
       40 . The method of  claim 35 , after removing the hard mask pattern and the pad oxide pattern, further comprising removing a portion of the second device isolation pattern to partially expose sidewalls of the first conductive pattern. 
   
   
       41 . The method of  claim 35 , after forming a dielectric layer and a second conductive pattern, further comprising supplying hydrogen (H) gas onto the substrate to trap hydrogen atoms in the interface traps between the substrate and the tunnel oxide pattern.