Plateline Driver with Ramp Rate Control

Abstract

A memory circuit and method to reduce wordline coupling is disclosed. The circuit includes a plurality of memory cells arranged in rows ( 702, 704, and 706 ) and columns ( 750, 752 ). A first conductor ( 710, 850 ) is coupled to a plurality of the rows ( 702, 704, and 706 ) of memory cells. A first transistor ( 810 ) has a current path coupled between a voltage supply terminal ( 800 ) and the first conductor ( 850 ) and a control terminal coupled to receive a first control signal (PLV). A second transistor ( 820 ) has a current path coupled between the voltage supply terminal and the first conductor and a control terminal coupled to receive a second control signal (PLW).

1 - 15 . (canceled)  
   
   
       16 . A method of reducing voltage coupled from a first conductor to a second conductor of a memory circuit, comprising the steps of: 
 activating the first conductor at a first rate of change of voltage with respect to time for a first time to couple a first logic level to the second conductor; and    activating the first conductor at a second rate of change of voltage with respect to time greater than the first rate of change of voltage with respect to time for a second time to produce a second logic level of the second conductor.    
   
   
       17 . A method as in  claim 16 , wherein the memory circuit comprises a plurality of nonvolatile memory cells.  
   
   
       18 . A method as in  claim 16 , wherein the first conductor is a plateline conductor and the second conductor is a wordline conductor.  
   
   
       19 . A method as in  claim 16 , comprising the step of: 
 activating the first conductor at a third rate of change of voltage with respect to time for a third time after the second time to produce the first logic level.    
   
   
       20 . A method as in  claim 19 , wherein the first and second rates of change of voltage with respect to time are positive, and wherein the third rate of change of voltage with respect to time is negative.  
   
   
       21 . A method as in  claim 19 , comprising the steps of: 
 activating the first conductor for a fourth time after the third time at a fourth rate of change of voltage with respect to time.    
   
   
       22 . A method as in  claim 21 , wherein the fourth rate of change of voltage with respect to time is positive.  
   
   
       23 . A method as in  claim 21 , wherein the fourth rate of change of voltage with respect to time is less than the first rate of change of voltage with respect to time.  
   
   
       24 . A method as in  claim 21 , wherein the fourth rate of change of voltage with respect to time is equal to the first rate of change of voltage with respect to time.  
   
   
       25 . A method as in  claim 21 , wherein the fourth rate of change of voltage with respect to time is greater than the first rate of change of voltage with respect to time.  
   
   
       26 - 36 . (canceled)