Method and structure to enhance temperature/humidity/bias performance of semiconductor devices by surface modification

Abstract

A method is disclosed of repairing wirebond damage on semiconductor chips such as high speed semiconductor microprocessors, application specific integrated circuits (ASICs), and other high speed integrated circuit devices, particularly devices using low-k dielectric materials. The method involves surface modification using reactive liquids. In a preferred embodiment, the method comprises applying a silicon-containing liquid reagent precursor such as TEOS to the surface of the chip and allowing the liquid reagent to react with moisture to form a solid dielectric plug or film ( 50 ) to produce a barrier against moisture ingress, thereby enhancing the temperature/humidity/bias (THB) performance of such semiconductor devices.

1 . An integrated circuit chip comprising: 
 a first dielectric material ( 35 ) at the top surface of said integrated circuit chip;    electrical connections ( 20 ) attached to the top surface of said integrated circuit chip; and    a layer of a second dielectric material ( 50 ) atop the top surface of said integrated circuit chip, wherein said second dielectric material is a silicon-containing conformal encapsulant.    
     
     
         2 . The integrated circuit chip of  claim 1 , wherein said electrical connections ( 20 ) are wire bonds.  
     
     
         3 . The integrated circuit chip of  claim 1 , wherein said electrical connections ( 20 ) are soldered connections attaching the chip to a chip carrier, interposer, or ceramic package.  
     
     
         4 . The integrated circuit chip of  claim 1 , wherein said first dielectric material ( 35 ) at the top surface contains microcracks ( 40 ), and said second dielectric material ( 50 ) conformally fills the microcracks ( 40 ).  
     
     
         5 . The integrated circuit chip of  claim 4 , wherein the microcracks ( 40 ) have a width of 1 micron or less, and a depth of 10 microns or less.  
     
     
         6 . The integrated circuit chip of  claim 4 , wherein the microcracks ( 40 ) have a width of about 0.5 micron, and a depth of about 1 to about 5 microns.  
     
     
         7 . The integrated circuit chip of  claim 1 , wherein the integrated circuit chip contains a delamination beneath said first dielectric material ( 35 ), and said second dielectric material ( 50 ) conformally fills the delamination.  
     
     
         8 . The integrated circuit chip of  claim 1 , wherein the second dielectric material ( 50 ) comprises a reactive, low viscosity, silicon-containing material selected from the group consisting of alkoxy silanes, siloxanes, silazanes, epoxy-siloxanes (including alkoxy-epoxy-siloxanes), epoxy-silazanes, urea-silazanes, carbo-silazanes, urea-siloxanes, carbo-siloxanes, polysilazanes, polyureasilazanes, polycarbosilazanes, polysiloxanes, polyureasiloxanes, polycarbosiloxanes, related silicon-containing polymers, TEOS (tetra ethoxysilane tetraorthosilicate), HMDS (hexamethyldisilazane), TMCTS (tetra methyl cyclo tetra siloxane) and 3MC3S (tri methyl cyclo tri siloxane).