Electronic system modules and method of fabricaton

Abstract

This specification describes techniques for manufacturing an electronic system module. The module includes flexible multi-layer interconnection circuits with trace widths as narrow as 5 microns or less. A glass panel manufacturing facility, similar to those employed for making liquid crystal display, LCD, panels is preferably used to fabricate the interconnection circuits. A multi-layer interconnection circuit is fabricated on the glass panel using a release layer. A special assembly layer is formed over the interconnection circuit comprising a thick dielectric layer with openings formed at input/output (I/O) pad locations. Solder paste is deposited in the openings using a squeegee to form wells filled with solder. IC chips are provided with gold stud bumps at I/O pad locations, and these bumps are inserted in the wells to form flip chip connections. The IC chips are tested and reworked. The same bump/well connections can be used to attach fine-pitch cables. Module packaging layers are provided for hermetic sealing and for electromagnetic shielding. A blade server or supercomputer embodiment is also described.

1 . An interconnect assembly comprising: 
 a base layer;    an interconnection circuit fabricated on said base layer comprising one or more layers of conductive traces with intervening dielectric material, said interconnection circuit having exposed input/output pads on a top layer, wherein said input/output pads are connected to selected ones of said conductive traces in said interconnection circuit;    an additional layer of dielectric material fabricated on top of said interconnection circuit that is patterned to create wells at each of said input/output pads; and    conductive material filling said wells.    
   
   
       2 . The interconnect assembly of  claim 1  wherein said base layer is flexible.  
   
   
       3 . The interconnect assembly of claim I wherein said base layer is rigid.  
   
   
       4 . The interconnect assembly of  claim 3  wherein said rigid base layer is a glass substrate.  
   
   
       5 . The interconnect assembly of  claim 1  wherein said base layer is a silicon wafer.  
   
   
       6 . The interconnect assembly of  claim 1  wherein said conductive traces have a minimum pitch of 20 microns or less.  
   
   
       7 . The interconnect assembly of claim I wherein said wells are spaced apart with a minimum pitch of less than 200 microns.  
   
   
       8 . The interconnect assembly of  claim 1  wherein said conductive material filling said wells includes solder.  
   
   
       9 . The interconnect assembly of claim I wherein said conductive material filling said wells is an indium-based solder such as Indalloy 290 containing 97% In and 3% Ag.  
   
   
       10 . An electronic assembly comprising: 
 a base layer;    one or more electronic components having a conductive bump at each input/output pad of each of said components;    an interconnection circuit fabricated on said base layer comprising one or more layers of conductive traces with intervening dielectric material, said interconnection circuit having at least one exposed input/output pad on a top layer for each of said bumps, wherein said input/output pads are connected to selected ones of said conductive traces in said interconnection circuit; surface depressions forming wells at each of said input/output pads; and    conductive material filling said wells;    wherein said bumps are mated with said conductive material filling said wells to mechanically attach and electrically connect said electronic components to said interconnection circuit at said input/output pads of said interconnection circuit.    
   
   
       11 . An electronic assembly comprising: 
 a base layer,    one or more electronic components having a conductive bump at each input/output pad of each of said components;    an interconnection circuit fabricated on said base layer comprising one or more layers of conductive traces with intervening dielectric material, said interconnection circuit having exposed input/output pads on a top layer, wherein said input/output pads are connected to selected ones of said conductive traces in said interconnection circuit;    an additional layer of dielectric material fabricated on top of said interconnection circuit that is patterned to create wells at each of said input/output pads; and    conductive material filling said wells;    wherein said bumps are mated with said conductive material filling said wells to mechanically attach and electrically connect said electronic components to said interconnection circuit at said input/output pads of said interconnection circuit.    
   
   
       12 . An electronic assembly comprising: 
 a base layer;    one or more electronic components having a conductive bump at each input/output pad of each of said components;    one or more access cables having a conductive bump at each input/output pad of each of said access cables;    an interconnection circuit fabricated on said base layer comprising one or more layers of conductive traces with intervening dielectric material, said interconnection circuit having exposed input/output pads on a top layer, wherein said input/output pads are connected to selected ones of said conductive traces in said interconnection circuit;    an additional layer of dielectric material fabricated on top of said interconnection circuit that is patterned to create wells at each of said input/output pads; and    conductive material filling said wells;    wherein said bumps of said components and said bumps of said access cables are mated with said conductive material filling said wells to mechanically attach and electrically connect said components and said access cables to said interconnection circuit at said input/output pads of said interconnection circuit.    
   
   
       13 . The electronic assembly of claims  10  wherein said electronic components are integrated circuit chips in bare die form.  
   
   
       14 . The electronic assembly of claims  10  wherein said conductive bumps are stud bumps.  
   
   
       15 . The electronic assembly of  claim 10  wherein said electronic components are thermally coupled to a heat sink.  
   
   
       16 . The electronic assembly of  claim 15  wherein said thermal coupling includes a thin layer of thermally conductive material between faces of said components or films covering said faces and a surface of said heat sink.  
   
   
       17 . An electronic assembly comprising: 
 an interconnection circuit having wells filled with conductive material at some or all of its input/output pads; and,    one or more module access cables having a conductive bump at some or all of its input/output pads;    wherein said conductive bumps are mated with said wells of said interconnection circuit in a one to one relationship.    
   
   
       18 . An electronic assembly comprising: 
 an interconnection circuit having wells filled with conductive material at some or all of its input/output pads;    one or more components having a conductive bump at some or all of its input/output pads; and    one or more module access cables having a conductive bump at some or all of its input/output pads;    wherein said conductive bumps of said components and said module access cables are mated with said wells of said interconnection circuit in a one to one relationship.    
   
   
       19 . An electronic cable having built-in connection means comprising: 
 a base layer;    an interconnection circuit fabricated on said base layer, said interconnection circuit including conductive traces;    wherein said traces terminate at bonding pads of said cable, and said bonding pads are arrayed to form cable ports with at least one input port and at least one output port per cable;    wherein each of said ports includes a connection means at each of said bonding pads; and,    wherein said connection means is implemented using either conductive bumps or wells filled with conductive material.    
   
   
       20 . The electronic cable of  claim 19  wherein said cable is formed into multiple fingers and each of said fingers includes one or more of said ports.  
   
   
       21 . The electronic cable of  claim 19  wherein one or more of said ports has a redistributed array of said bonding pads, with increased spacing between said pads.  
   
   
       22 . A stacked contact formed between a plurality of conductive layers of an interconnection circuit comprising: 
 planarizing layers of dielectric material between each of said conductive layers; and    contact windows having tapered walls in each of said planarizing layers, said contact windows positioned above connection points on preceding metal layers and below connection points on succeeding metal layers.    
   
   
       23 . The stacked contact of  claim 22  wherein said contact windows are photo-defined.  
   
   
       24 . The stacked contact of  claim 22  wherein trace stubs are provided at each conducting layer of the stacked contact.  
   
   
       25 . A multi-layer interconnection circuit wherein stacked contacts with trace stubs are provided at input/output pads of said interconnection circuit.  
   
   
       26 . A circuit assembly comprising: 
 a plurality of integrated circuits having conductive bumps at each input/output pad;    an interconnection circuit having wells filled with solder, said wells corresponding in a one-to-one relationship with said conductive bumps of said integrated circuits; and    bonding at each of said pads said conductive bumps to said solder in each of said wells to form a permanent connection.    
   
   
       27 . The circuit assembly of  claim 26  wherein said interconnection circuit is flexible.  
   
   
       28 . A circuit assembly that may be reworked to replace a defective component, comprising: 
 a base layer;    an interconnection circuit having input/output pads fabricated on said base layer;    wells filled with solder fabricated on said interconnection circuit at said input/output pads;    components having conductive bumps at connection points; and    wherein said conductive bumps are mated with said wells filled with solder to form re-workable bonds.    
   
   
       29 . A module access port for an electronic module comprising: 
 a set of module access pads;    a well formed from dielectric material at each of said module access pads; and    conductive material filling each of said wells.    
   
   
       30 . A hermetically sealed electronic circuit module having attached components comprising: 
 a module access port including an array of module access pads;    a dielectric layer coating said circuit module at surfaces having attached components, with openings at said module access pads; and    a continuous metal film coating the entire surface of said circuit module, except for said openings at said module access pads.    
   
   
       31 . An electro-magnetically shielded electronic circuit module having attached components comprising: 
 a module access port including an array of module access pads;    a dielectric layer coating said circuit module at surfaces having attached components with openings at said module access pads; and    a continuous metal film coating the entire surface of said circuit module, except for said openings at said module access pads.    
   
   
       32 . The electro-magnetically shielded circuit module of  claim 31  wherein said continuous metal film is grounded.