Semiconductor device and method of manufacturing the same
Abstract
A semiconductor device is provided comprising a supporting substrate, an insulating layer on the substrate, and a first semiconductor layer on the insulating layer. A first high breakdown-voltage transistor is formed in the first semiconductor layer, a second semiconductor layer is formed on the insulating layer and a second high breakdown-voltage transistor is formed in the second semiconductor layer. A first element isolation region reaching the insulating layer is provided between the first and second semiconductor layers. A third semiconductor layer is formed on the insulating layer, a first low breakdown-voltage transistor is formed in the third semiconductor layer, a second low breakdown-voltage transistor is formed in the third semiconductor layer, and a second element isolation region not reaching the insulating layer is formed in the third semiconductor layer between the first and second low breakdown-voltage transistors. The first element isolation region comprises a dual-trench insulating layer.
Claims
exact text as granted — not AI-modified1 . A semiconductor device, comprising:
a first transistor that includes a first gate insulating film having a first thickness; a second transistor that includes a second gate insulating film having a second thickness; a first isolation region having a first depth; a second isolation region having a second depth; a third isolation region having a third depth; and a fourth isolation region having a fourth depth, the first transistor being disposed between the first isolation region and the second isolation region, the second transistor being disposed between the third isolation region and the fourth isolation region, each of the first depth and the second depth being deeper than the third depth, and the first thickness being greater than the second thickness.
2 . A semiconductor device comprising:
a first transistor; a second transistor; a first isolation region having a first depth; a second isolation region having a second depth; a third isolation region having a third depth; and a fourth isolation region having a fourth depth, the first transistor being disposed between the first isolation region and the second isolation region, the second transistor being disposed between the third isolation region and the fourth isolation region, each of the first depth and the second depth being deeper than the third depth, and no isolation region being formed between the first isolation region and the second isolation region.
3 . A semiconductor device comprising:
a first transistor; a second transistor; and a plurality of isolation regions, the plurality of isolation regions including:
a first isolation region having a first depth;
a second isolation region having a second depth;
a third isolation region having a third depth; and
a fourth isolation region having a fourth depth,
the first transistor being disposed between the first isolation region and the second isolation region, the second transistor being disposed between the third isolation region and the fourth isolation region, each of the first depth and the second depth being deeper than the third depth, and the first isolation region being adjacent to the second isolation region among the plurality of isolation regions.
4 . The semiconductor device according to claim 3 ,
each of the first isolation region and the second isolation region having a dual-trench structure that includes a first trench and a second trench that has a width that is greater than a width of the first trench.
5 . The semiconductor device according to claim 3 , further comprising an insulating layer,
each of the first transistor, the second transistor, the first isolation region, and the second isolation region being formed above the insulating layer, and each of the first isolation region and the second isolation region contacting the insulating layer.
6 . The semiconductor device according to claim 3 , further comprising an insulating layer,
each of the first transistor, the second transistor, the first isolation region, and the second isolation region being formed above the insulating layer, and the third isolation region being separated from the insulating layer.
7 . The semiconductor device according to claim 3 ,
the first transistor including a third trench region covered by a first gate insulating film of the first transistor.
8 . The semiconductor device according to claim 7 ,
the third trench region having a depth equal to the third depth.
9 . The semiconductor device according to claim 3 ,
the third trench region and the third isolation region being formed by an identical process.
10 . A semiconductor device comprising:
a first transistor that includes a first gate insulating film having a first thickness; a second transistor that includes a second gate insulating film having a second thickness; a first isolation region having a first trench reaching a first depth; a second isolation region having a second trench reaching a second depth; a third isolation region having a third trench reaching a third depth; a fourth isolation region having a fourth trench reaching a fourth depth, the first trench, the second trench, the third trench and the fourth trench being formed in a semiconductor substrate in which the first transistor and the second transistor are formed, the first transistor being disposed between the first isolation region and the second isolation region, the second transistor being disposed between the third isolation region and the fourth isolation region, each of the first trench and the second trench being deeper than the third trench, and the first thickness being greater than the second thickness.Join the waitlist — get patent alerts
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