Semiconductor device and a method of manufacture therefor

Abstract

The present invention provides a semiconductor device, and an integrated circuit including the semiconductor device. The semiconductor device, in one embodiment, includes: ( 1 ) a gate structure located over a substrate, the gate structuring including a gate dielectric and gate electrode; ( 2 ) source/drain regions located within the substrate proximate the gate structure, ( 3 ) a multi layer etch stop located over the substrate, wherein the etch stop has a first insulative layer and a second silicon-rich nitride layer located over the first insulative layer, ( 4 ) a dielectric layer located over the etch stop, the dielectric layer having an opening formed therein that extends through at least a portion of the multi layer etch stop, ( 5 ) a conductive plug located within the opening and electrically contacting the gate electrode and one of the source/drain regions, and ( 6 ) an insulative spacer located between the conductive plug and the second silicon-rich nitride layer.

1 . A semiconductor device, comprising: 
 a gate structure located over a substrate, said gate structuring including a gate dielectric and gate electrode;    source/drain regions located within said substrate proximate said gate structure;    a multi layer etch stop located over said substrate, wherein said multi layer etch stop has a first insulative layer and a second silicon-rich nitride layer located over said first insulative layer;    a dielectric layer located over said multi layer etch stop, said dielectric layer having an opening formed therein that extends through at least a portion of said multi layer etch stop;    a conductive plug located within said opening and electrically contacting said gate electrode and one of said source/drain regions; and    an insulative spacer located between said conductive plug and said second silicon-rich nitride layer.    
   
   
       2 . The semiconductor device as recited in  claim 1  wherein said first insulative layer is a first silicon nitride portion.  
   
   
       3 . The semiconductor device as recited in  claim 2  wherein said first silicon nitride portion has a Si x  to N y  ratio (x:y) of 0.75 or less and said second silicon-rich nitride layer has a Si x  to N y  ratio (x:y) of greater than about 1.0.  
   
   
       4 . The semiconductor device as recited in  claim 3  wherein said second silicon-rich nitride layer is pure silicon.  
   
   
       5 . The semiconductor device as recited in  claim 1  wherein said insulative spacer is a silicon nitride insulative spacer.  
   
   
       6 . The semiconductor device as recited in  claim 5  wherein said silicon nitride insulative spacer has a Si x  to N y  ratio (x:y) of 0.75 or less.  
   
   
       7 . The semiconductor device as recited in  claim 1  wherein said insulative spacer has a maximum thickness ranging from about 10 nm to about 30 nm.  
   
   
       8 . The semiconductor device as recited in  claim 1  wherein a thickness of said insulative spacer tapers as said insulative spacer approaches said second silicon-rich nitride layer.  
   
   
       9 . An integrated circuit, comprising: 
 transistors located over a semiconductor substrate, each of said transistors including a gate dielectric and a gate electrode    source/drain regions located within said substrate proximate associated transistors;    a multi layer etch stop located over said transistors and said semiconductor substrate, wherein said multi layer etch stop has a first insulative layer and a second silicon-rich nitride layer located over said first insulative layer;    an interlevel dielectric layer located over said multi layer etch stop, said interlevel dielectric layer having openings formed therein for contacting said transistors, said openings extending through at least a portion of said multi layer etch stop;    conductive plugs located within said openings and electrically contacting associated ones of said gate electrodes and ones of said source/drain regions; and    insulative spacers located between said conductive plugs and said second silicon-rich nitride layer.    
   
   
       10 . The integrated circuit as recited in claim  17  wherein said first insulative layer is a first silicon nitride portion, and wherein said first silicon nitride portion has a Si x  to N y  ratio (x:y) of 0.75 or less and said second silicon-rich nitride layer has a Si x  to N y  ratio (x:y) of greater than about 1.0.  
   
   
       11 . The integrated circuit as recited in claim  17  wherein said insulative spacer is a silicon nitride insulative spacer, and further wherein said silicon nitride insulative spacer has a Si x  to N y  ratio (x:y) of 0.75 or less.  
   
   
       12 . The integrated circuit as recited in claim  17  wherein said transistors are selected from the group consisting of CMOS devices, BiCMOS devices, bipolar devices or combinations thereof.  
   
   
       13 . A semiconductor device, comprising: 
 a multi layer etch stop located over a substrate, wherein said multi layer etch stop has a first insulative layer and a second silicon-rich nitride layer located over said first insulative layer;    a dielectric layer located over said multi layer etch stop, said dielectric layer having an opening formed therein that extends through at least a portion of said multi layer etch stop, thereby providing a sidewall of said at least a portion of said multi layer etch stop;    a conductive plug located within said opening; and    an insulative spacer having a Si x  to N y  ratio (x:y) of 0.75 or less located between said conductive plug and said sidewall of said at least a portion of said multi layer etch stop.