Semiconductor integrated circuit device and method for designing the same

Abstract

A semiconductor integrated circuit device has a plurality of design patterns composed of circuit elements or wires formed on a substrate. The respective finished sizes of the plurality of design patterns have a plurality of minimum size values which differ from one design pattern to another depending on the geometric feature of each of the design patterns.

1 - 8 . (canceled)  
   
   
       9 . A semiconductor integrated circuit device comprising: 
 a plurality of design patterns composed of circuit elements or wires formed on a substrate, the plurality of design patterns having a plurality of minimum size values which differ from one design pattern to another depending on different finished sizes resulting from an electric specification of each of the design patterns and a designing means for implementing the electric specification.    
   
   
       10 . The semiconductor integrated circuit device of  claim 9 , wherein the plurality of minimum size values are set for a length or width of each of parts composing the circuit elements, a spacing between the parts, an overlapping portion between the parts, or a configuration of a protruding portion of the part and are set for a width of each of the wires or a spacing between the wires.  
   
   
       11 . The semiconductor integrated circuit device of  claim 9 , wherein the circuit elements are bit cells in a memory device and an area occupied by each of the bit cells is determined by any of the plurality of minimum size values.  
   
   
       12 . The semiconductor integrated circuit device of  claim 9 , wherein the circuit elements are contained in an element formation layer and the wires are contained in a wiring layer, the device further comprising: 
 one or more contacts for providing an electric connection between the element formation layer and the wiring layer,    the minimum size value of the finished size of each of the contacts depending on an area occupied by the contact on the substrate or on the number of the contacts.    
   
   
       13 . The semiconductor integrated circuit device of  claim 9 , wherein 
 the electric specification is suppression of a leakage current and    the designing means includes at least one of power voltage control, power shutdown control, threshold voltage control, and gate-to-source potential control.    
   
   
       14 . The semiconductor integrated circuit device of  claim 9 , wherein 
 the electric specification is an operating speed and    the designing means includes at least one of power voltage control, threshold voltage control, and delay control effected by using variations in the number of wiring layers used in a layout.    
   
   
       15 . The semiconductor integrated circuit device of  claim 9 , wherein 
 the electric specification is a timing value and    the designing means includes at least one of selection of synchronous design or asynchronous design, delay control effected by using variations in the number of wiring layers used in a layout, a delay circuit for timing adjustment, a gate size of a transistor, and a layout for adjusting a distance from a clock driver.    
   
   
       16 . The semiconductor integrated circuit device of  claim 9 , wherein 
 the circuit elements are memory elements and    the designing means is a means for imparting a redundancy function for saving a defect.    
   
   
       17 - 33 . (canceled)  
   
   
       34 . A method for designing a semiconductor integrated circuit device, the method comprising the step of: 
 forming, on a substrate, a plurality of design patterns composed of circuit elements or wires, wherein    a plurality of design rules having different values are applied to the plurality of design patterns depending on different finished sizes resulting from an electric specification of each of the design patterns and a designing method for implementing the electric specification.    
   
   
       35 . The method of  claim 34 , wherein the plurality of design rules are applied to a length or width of each of parts composing the circuit elements, a spacing between the parts, an overlapping portion between the parts, or a configuration of a protruding portion of the part and are applied to a width of each of the wires or a spacing between the wires.  
   
   
       36 . The method of  claim 34 , wherein the circuit elements are bit cells in a memory device and an area occupied by each of the bit cells is determined by any of the plurality of design rules.  
   
   
       37 . The method of  claim 34 , further comprising the step of: 
 forming one or more contacts for providing electric connections between the circuit elements and the wires, wherein    any of the plurality of design rules is applied by using dependence of the finished size of each of the contacts on an area occupied by the contact on the substrate or on the number of the contacts.    
   
   
       38 . The method  claim 34 , wherein 
 the electric specification is suppression of a leakage current and    the designing method includes at least one of power voltage control, power shutdown control, threshold voltage control, and gate-to-source potential control.    
   
   
       39 . The method of  claim 34 , wherein 
 the electric specification is an operating speed and    the designing method includes at least one of power voltage control, threshold voltage control, and delay control effected by using variations in the number of wiring layers used in a layout.    
   
   
       40 . The method  claim 34 , wherein 
 the electric specification is a timing value and    the designing method includes at least one of selection of synchronous design or asynchronous design, delay control effected by using variations in the number of wiring layers used in a layout, a delay circuit for timing adjustment, a gate size of a transistor, and a layout for adjusting a distance from a clock driver.    
   
   
       41 . The method  claim 34 , wherein 
 the circuit elements are memory elements and    the designing method is a method for imparting a redundancy function for saving a defect.    
   
   
       42 - 50 . (canceled)