Semiconductor package comprising alignment members

Abstract

A semiconductor package comprising alignment members is provided. The semiconductor package includes a semiconductor die, first connection terminals disposed on a first surface of the semiconductor die, and a tape substrate including a substrate portion, and second connection terminals disposed on the substrate portion and disposed corresponding to the first connection terminals. The semiconductor package further includes a first alignment member disposed on the first surface of the semiconductor die, and a second alignment member disposed on the substrate portion of the tape substrate and disposed corresponding to the first alignment member.

1 . A semiconductor package comprising:
 a semiconductor die;   first connection terminals disposed on a first surface of the semiconductor die;   a tape substrate comprising a substrate portion, and second connection terminals disposed on the substrate portion and disposed corresponding to the first connection terminals;   a first alignment member disposed on the first surface of the semiconductor die; and,   a second alignment member disposed on the substrate portion of the tape substrate and disposed corresponding to the first alignment member.   
   
   
       2 . The semiconductor package of  claim 1 , wherein the tape substrate is a chip on film type of tape automated bonding (TAB) tape substrate. 
   
   
       3 . The semiconductor package of  claim 1 , wherein the first alignment member has the same shape as at least one of the first connection terminals and at least a portion of the second alignment member has the same shape as at least one of the second connection terminals. 
   
   
       4 . The semiconductor package of  claim 1 , wherein the first alignment member is disposed at a center portion of the first surface of the semiconductor die or on a portion of the first surface of the semiconductor die where the first connection terminals are disposed. 
   
   
       5 . The semiconductor package of  claim 1 , wherein:
 the first alignment member comprises a dummy bump;   the second alignment member comprises a pair of dummy leads; and,   at least a portion of the dummy bump is interposed between the dummy leads.   
   
   
       6 . The semiconductor package of  claim 1 , wherein:
 the first alignment member comprises a pair of dummy bumps;   the second alignment member comprises a dummy lead; and,   at least a portion of the dummy lead is interposed between the dummy bumps.   
   
   
       7 . The semiconductor package of  claim 1 , wherein:
 the first alignment member comprises a cylindrical dummy pattern; and,   the second alignment member comprises an annular dummy pattern surrounding at least a portion of the cylindrical dummy pattern.   
   
   
       8 . The semiconductor package of  claim 1 , wherein:
 the second alignment member comprises a cone-like dummy pattern; and,   the first alignment member comprises an annular dummy pattern surrounding at least a portion of the second alignment member.   
   
   
       9 . The semiconductor package of  claim 1 , wherein a gap between a side surface of the first alignment member and a side surface of the second alignment member is less than about 2 μm. 
   
   
       10 . The semiconductor package of  claim 1 , wherein a side surface of the first alignment member is in contact with a side surface of the second alignment member. 
   
   
       11 . The semiconductor package of  claim 1 , wherein;
 the first connection terminals comprise a plurality of first bumps disposed along a first edge of the semiconductor die and a plurality of second bumps disposed along a second edge of the semiconductor die; and,   the second connection terminals comprise a plurality of first inner leads disposed corresponding to the first bumps and a plurality of second inner leads disposed corresponding to the second bumps.   
   
   
       12 . The semiconductor package of  claim 11 , wherein the first alignment member is disposed between two of at least one of the first bumps or the second bumps, and the second alignment member is disposed between inner leads of the first inner leads or the second inner leads. 
   
   
       13 . The semiconductor package of  claim 12 , wherein:
 the first alignment member comprises a dummy bump having the same shape as at least one of the first bumps or second bumps; and,   the second alignment member comprises a dummy inner lead having the same shape as at least one of one inner leads of the first inner leads or the second inner leads.   
   
   
       14 . The semiconductor package of  claim 12 , wherein:
 the first alignment member comprises a pair of dummy bumps;   the second alignment member comprises a dummy lead; and,   at least a portion of the dummy lead is interposed between the dummy bumps.   
   
   
       15 . The semiconductor package of  claim 12 , wherein:
 the first alignment member comprises a cylindrical dummy pattern; and,   the second alignment member comprises an annular dummy pattern surrounding at least a portion of the first alignment member.   
   
   
       16 . The semiconductor package of  claim 12 , wherein:
 the second alignment member comprises a cone-like dummy pattern; and,   the first alignment member comprises an annular dummy pattern surrounding at least a portion of the second alignment member.   
   
   
       17 . The semiconductor package of  claim 12 , wherein a side surface of the first alignment member is in contact with a side surface of the second alignment member. 
   
   
       18 . The semiconductor package of  claim 12 , wherein a gap between a side surface of the first alignment member and a side surface of the second alignment member is less than about 2 μm. 
   
   
       19 . A semiconductor package comprising:
 a semiconductor die;   first connection terminals disposed on a first surface of the semiconductor die;   a tape substrate comprising a substrate portion, and second connection terminals disposed on the substrate portion and disposed corresponding to the first connection terminals;   a first alignment member disposed on the first surface of the semiconductor die; and,   a second alignment member disposed on the substrate portion of the tape substrate,   wherein at least a portion of the first alignment member is disposed between portions of the second alignment member.   
   
   
       20 . A semiconductor package comprising:
 a semiconductor die;   first connection terminals disposed on a first surface of the semiconductor die;   a tape substrate comprising a substrate portion, and second connection terminals disposed on the substrate portion and disposed corresponding to the first connection terminals;   a first alignment member disposed on the first surface of the semiconductor die; and,   a second alignment member disposed on the substrate portion of the tape substrate,   wherein at least a portion of the second alignment member is disposed between portions of the first alignment member.