Mos transistor in an active region
Abstract
After an isolation region is formed using a field-forming silicon nitride film, this silicon nitride film is patterned, thereby a gate trench is formed. Next, a gate electrode material is buried into the gate trench, and this is etched back. Thereafter, the silicon nitride is removed, thereby a contact hole is formed. A contact plug is buried into this contact hole. With this arrangement, the contact plug can be formed without using a diffusion layer contact pattern. At the same time, the periphery of the contact plug substantially coincides with a boundary between the element isolation region and the active region. Accordingly, the active region can be reduced.
Claims
exact text as granted — not AI-modified1 - 6 . (canceled)
7 . A method of manufacturing a semiconductor device, comprising:
a first step for forming a field-forming insulation film having a predetermined pattern on a semiconductor substrate; a second step for forming an isolation region using the field-forming insulation film; a third step for forming a gate trench by patterning at least the field-forming insulation film; a fourth step for burying at least a gate electrode into the gate trench; a fifth step for forming a contact hole by removing the field-forming insulation film; and a sixth step for burying a contact plug into the contact hole.
8 . The method of manufacturing a semiconductor device as claimed in claim 7 , wherein said second step includes:
a first sub-step for forming an isolation trench on the semiconductor substrate using the field-forming insulation film as a mask; and a second sub-step for burying a dielectric material into the isolation trench.
9 . The method of manufacturing a semiconductor device as claimed in claim 7 , wherein said fourth step includes:
a third sub-step for forming a sidewall made of a dielectric material on a side surface of the gate trench; a fourth sub-step for burying a conductive material into the gate trench; and a fifth sub-step for forming the gate electrode by removing an unnecessary portion of the conductive material.
10 . The method of manufacturing a semiconductor device as claimed in claim 9 , wherein said conductive material is removed so that the upper surface of the gate electrode becomes lower than the upper surface of the field-forming insulation film in the fifth sub-step.
11 . The method of manufacturing a semiconductor device as claimed in claim 9 , wherein a dielectric material that constitutes the sidewall is different from a material of the field-forming insulation film.
12 . The method of manufacturing a semiconductor device as claimed in claim 9 , wherein said fourth step further includes a sixth sub-step of forming a cap made of a dielectric material on an upper surface of the gate electrode.
13 . The method of manufacturing a semiconductor device as claimed in claim 12 , wherein
at the sixth sub-step, after a dielectric film that covers the field-forming insulation film and the gate electrode is formed, the dielectric film is polished until when an upper surface of the field-forming insulation film is exposed.
14 . The method of manufacturing a semiconductor device as claimed in claim 12 , wherein a dielectric material that constitutes the cap is different from a material of the field-forming insulation film.
15 . The method of manufacturing a semiconductor device as claimed in claim 7 , wherein a material of the field-forming insulation film is silicon nitride.
16 . The method of manufacturing a semiconductor device as claimed in claim 11 , wherein a material of the field-forming insulation film is silicon nitride.
17 . The method of manufacturing a semiconductor device as claimed in claim 16 , wherein a material of the sidewall is silicon oxide.
18 . The method of manufacturing a semiconductor device as claimed in claim 14 , wherein a material of the field-forming insulation film is silicon nitride.
19 . The method of manufacturing a semiconductor device as claimed in claim 18 , wherein a material of the cap is silicon oxide.Join the waitlist — get patent alerts
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