STRUCTURE AND METHOD TO OPTIMIZE STRAIN IN CMOSFETs

Abstract

A semiconductor structure of strained MOSFETs, comprising both PMOSFETs and NMOSFETS, and a method for fabricating strained MOSFETs are disclosed that optimize strain in the MOSFETs, and more particularly maximize the strain in one kind (P or N) of MOSFET and minimize and relax the strain in another kind (N or P) of MOSFET. A strain inducing CA nitride coating having an original full thickness is formed over both the PMOSFETs and the NMOSFETs, wherein the strain inducing coating produces an optimized full strain in one kind of semiconductor device and degrades the performance of the other kind of semiconductor device. The strain inducing CA nitride coating is etched to a reduced thickness over the other kind of semiconductor devices, wherein the reduced thickness of the strain inducing coating relaxes and produces less strain in the other MOSFETs.

1 . A method of fabricating a semiconductor structure having a p-semiconductor device and an n-semiconductor device with different amounts of strain in the p-semiconductor device and the n-semiconductor device comprising: 
 forming a p-semiconductor device and an n-semiconductor device on a substrate;    forming a strain inducing coating having an original thickness over the p-semiconductor device and also over the n-semiconductor device, wherein the strain inducing coating produces strain in the p-semiconductor device and also in the n-semiconductor device;    protecting one of the strain inducing coated p-semiconductor device and strain inducing coated n-semiconductor device while the other strain inducing coated semiconductor device remains exposed;    etching the exposed strain inducing coating to reduce the thickness of the strain inducing coating to relax the strain in the exposed semiconductor device, while the strain inducing coating over the protected semiconductor device remains protected such that the strain in the protected semiconductor device remains unchanged.    
     
     
         2 . The method of  claim 1 , wherein following the etching, implanting a strain reducing dopant into the exposed semiconductor device to further relax the strain in the exposed semiconductor device.  
     
     
         3 . The method of  claim 2 , including implanting a strain reducing dopant comprising As or Ge.  
     
     
         4 . The method of  claim 3 , including implanting the As or Ge at a dosage of approximately 5e14 atoms/cm 2  to approximately 2e15 atoms/cm 2  at an implant energy of approximately 20 KeV to about 50 KeV.  
     
     
         5 . The method of  claim 1 , wherein said step of protecting comprises: 
 blanket depositing a photoresist layer over the p-semiconductor device and the n-semiconductor device on the substrate;    exposing the photoresist layer to a pattern of radiation and developing the pattern into the photoresist layer to provide a block mask overlying the protected semiconductor device.    
     
     
         6 . The method of  claim 1 , wherein said strain inducing coating provides a compressive strain to improve the performance of the protected p-semiconductor device and the compressive strain is relaxed in the exposed n-semiconductor device.  
     
     
         7 . The method of  claim 6 , wherein the p-semiconductor device is a p-type MOSFET and the n-semiconductor device is an n-type MOSFET.  
     
     
         8 . The method of  claim 1 , wherein said strain inducing coating provides a tensile strain to improve the performance of the protected n-semiconductor device and the compressive strain is relaxed in the exposed p-semiconductor device.  
     
     
         9 . The method of  claim 8 , wherein the p-semiconductor device is a p-type MOSFET and the n-semiconductor device is an n-type MOSFET.  
     
     
         10 . The method of  claim 1 , wherein the strain inducing coating comprises Si 3 N 4 .